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| MC68HC05C8A MC68HCL05C8A MC68HSC05C8A Technical Data M68HC05 Microcontrollers MC68HC05C8A/D Rev. 5, 4/2002 WWW.MOTOROLA.COM/SEMICONDUCTORS MC68HC05C8A MC68HCL05C8A MC68HSC05C8A Technical Data To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://www.motorola.com/semiconductors/ The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location. Motorola and the Stylized M Logo are registered trademarks of Motorola, Inc. DigitalDNA is a trademark of Motorola, Inc. (c) Motorola, Inc., 2002 MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 MOTOROLA Technical Data 3 Revision History Revision History Date April, 2002 Revision Level 5.0 Description Corrected World Wide Web address and qualification status Page Number(s) N/A Technical Data 4 MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 MOTOROLA Technical Data -- MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A List of Sections Section 1. General Description . . . . . . . . . . . . . . . . . . . . 19 Section 2. Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 mory Section 3. Central Processor Unit (CPU) . . . . . . . . . . . . 37 Section 4. Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Section 5. Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Section 6. Low-Power Modes. . . . . . . . . . . . . . . . . . . . . . 51 Section 7. Input/Output (I/O) Ports . . . . . . . . . . . . . . . . . 55 /Output Section 8. Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Section 9. Serial Communications Interface (SCI) . . . . . 69 Section 10. Serial Peripheral Interface (SPI). . . . . . . . . . 87 Section 11. Operating Modes . . . . . . . . . . . . . . . . . . . . . . 97 Section 12. Instruction Set . . . . . . . . . . . . . . . . . . . . . . . 103 2. Section 13. Electrical Specifications. . . . . . . . . . . . . . . 121 Section 14. Mechanical Specifications . . . . . . . . . . . . . 137 Section 15. Ordering Information . . . . . . . . . . . . . . . . . 141 Appendix A. MC68HCL05C8A . . . . . . . . . . . . . . . . . . . . 145 HCL05C8A Appendix B. MC68HSC05C8A . . . . . . . . . . . . . . . . . . . . 149 Appendix C. M68HC05Cx Family Feature Comparisons . . . . . . . . . . . . . . . . . . . . . 155 MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 MOTOROLA List of Sections Technical Data 5 List of Sections Technical Data 6 MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 List of Sections MOTOROLA Technical Data -- MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A Table of Contents Section 1. General Description 1.1 1.2 1.3 1.4 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Mask Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 1.5 Functional Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 1.5.1 VDD and VSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 1.5.2 IRQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 1.5.3 OSC1 and OSC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 1.5.4 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 1.5.5 TCAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 1.5.6 TCMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 1.5.7 Port A (PA0-PA7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 1.5.8 Port B (PB0-PB7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 1.5.9 Port C (PC0-PC7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 1.5.10 Port D (PD0-PD5 and PD7). . . . . . . . . . . . . . . . . . . . . . . . . 27 Section 2. Memory 2.1 2.2 2.3 2.4 2.5 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Read-Only Memory (ROM). . . . . . . . . . . . . . . . . . . . . . . . . . . .29 ROM Security Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Random-Access Memory (RAM) . . . . . . . . . . . . . . . . . . . . . . . 30 MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 MOTOROLA Table of Contents Technical Data 7 Table of Contents Section 3. Central Processor Unit (CPU) 3.1 3.2 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.3 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.3.1 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.3.2 Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.3.3 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.3.4 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.3.5 Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Section 4. Interrupts 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Hardware Controlled Interrupt Sequence . . . . . . . . . . . . . . . . . 43 Software Interrupt (SWI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 External Interrupt (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Timer Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Serial Communications Interrupt (SCI) . . . . . . . . . . . . . . . . . . . 45 Serial Peripheral Interrupt (SPI) . . . . . . . . . . . . . . . . . . . . . . . .46 Section 5. Resets 5.1 5.2 5.3 5.4 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Power-On Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 RESET Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 5.5 Computer Operating Properly (COP) Reset . . . . . . . . . . . . . . . 48 5.5.1 Resetting the COP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 5.5.2 COP During Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 5.5.3 COP During Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 5.5.4 COP During Self-Check Mode . . . . . . . . . . . . . . . . . . . . . . . 49 Technical Data 8 MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 Table of Contents MOTOROLA Table of Contents Section 6. Low-Power Modes 6.1 6.2 6.3 6.4 6.5 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Stop Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Section 7. Input/Output (I/O) Ports 7.1 7.2 7.3 7.4 7.5 7.6 7.7 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Input/Output Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 Section 8. Timer mer 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Output Compare Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Input Capture Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 Timer Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 Timer Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Timer During Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Timer During Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 MOTOROLA Table of Contents Technical Data 9 Table of Contents Section 9. Serial Communications Interface (SCI) 9.1 9.2 9.3 9.4 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 SCI Data Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 9.5 SCI Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 9.5.1 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 9.5.1.1 Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 9.5.1.2 Character Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . 72 9.5.1.3 Break Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 9.5.1.4 Idle Characters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 9.5.1.5 Transmitter Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . .74 9.5.2 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 9.5.2.1 Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 9.5.2.2 Character Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 9.5.2.3 Receiver Wakeup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 9.5.2.4 Receiver Noise Immunity . . . . . . . . . . . . . . . . . . . . . . . . . 77 9.5.2.5 Framing Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 9.5.2.6 Receiver Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 9.6 SCI Input/Output (I/O) Registers. . . . . . . . . . . . . . . . . . . . . . . . 78 9.6.1 SCI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 9.6.2 SCI Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 9.6.3 SCI Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 9.6.4 SCI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 9.6.5 Baud Rate Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Section 10. Serial Peripheral Interface (SPI) 10.1 10.2 10.3 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 10.4 SPI Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 10.4.1 Master In Slave Out (MISO) . . . . . . . . . . . . . . . . . . . . . . . . . 88 10.4.2 Master Out Slave In (MOSI) . . . . . . . . . . . . . . . . . . . . . . . . . 88 Technical Data 10 MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 Table of Contents MOTOROLA Table of Contents 10.4.3 10.4.4 10.5 Serial Clock (SCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Slave Select (SS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 10.6 SPI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 10.6.1 Serial Peripheral Control Register . . . . . . . . . . . . . . . . . . . . 93 10.6.2 Serial Peripheral Status Register . . . . . . . . . . . . . . . . . . . . .94 10.6.3 Serial Peripheral Data I/O Register . . . . . . . . . . . . . . . . . . . 96 Section 11. Operating Modes 11.1 11.2 11.3 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 User Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 11.4 Self-Check Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 11.4.1 Self-Check Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 11.4.2 Self-Check Results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Section 12. Instruction Set 12.1 12.2 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 12.3 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 12.3.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 12.3.2 Immediate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 12.3.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 12.3.4 Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 12.3.5 Indexed, No Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 12.3.6 Indexed, 8-Bit Offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 12.3.7 Indexed, 16-Bit Offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 12.3.8 Relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 12.4 Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 12.4.1 Register/Memory Instructions. . . . . . . . . . . . . . . . . . . . . . . 108 12.4.2 Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . . 109 12.4.3 Jump/Branch Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . 110 12.4.4 Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . .112 MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 MOTOROLA Table of Contents Technical Data 11 Table of Contents 12.4.5 12.5 12.6 Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Section 13. Electrical Specifications 13.1 13.2 13.3 13.4 13.5 13.6 13.7 13.8 13.9 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122 Operating Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . 122 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Power Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 5.0-V DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . 125 3.3-V DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . 126 5.0-V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129 . . . . . . . . . . . . . . . 132 . . . . . . . . . . . . . . . 133 13.10 3.3-V Control Timing 13.11 5.0-V Serial Peripheral Interface Timing 13.12 3.3-V Serial Peripheral Interface Timing Section 14. Mechanical Specifications 14.1 14.2 14.3 14.4 14.5 14.6 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 40-Pin Plastic Dual In-Line (DIP) Package (Case 711-03) . . . 138 42-Pin Plastic Shrink Dual In-Line (SDIP) Package (Case 858-01). . . . . . . . . . . . . . . . . . . . . . . . . . .138 44-Lead Plastic Leaded Chip Carrier (PLCC) (Case 777-02). 139 44-Lead Quad Flat Pack (QFP) (Case 824A-01) . . . . . . . . . . 140 Technical Data 12 MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 Table of Contents MOTOROLA Table of Contents Section 15. Ordering Information 5. 15.1 15.2 15.3 15.4 15.5 15.6 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 MCU Ordering Forms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 Application Program Media. . . . . . . . . . . . . . . . . . . . . . . . . . .142 ROM Program Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 ROM Verification Units (RVUs). . . . . . . . . . . . . . . . . . . . . . . . 143 Appendix A. MC68HCL05C8A A.1 A.2 A.3 A.4 A.5 A.6 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 Low-Power Operating Temperature Range . . . . . . . . . . . . . . 145 2.5-V to 3.6-V DC Electrical Characteristics . . . . . . . . . . . . . 146 1.8-V to 2.4-V DC Electrical Characteristics . . . . . . . . . . . . . . 146 Low-Power Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Appendix B. MC68HSC05C8A B.1 B.2 B.3 B.4 B.5 B.6 B.7 B.8 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 High-Speed Operating Temperature Range. . . . . . . . . . . . . . 149 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 150 4.5-V to 5.5-V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . 151 2.4-V to 3.6-V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . 152 4.5-V to 5.5-V High-Speed SPI Timing . . . . . . . . . . . . . . . . . . 153 2.4-V to 3.6-V High-Speed SPI Timing . . . . . . . . . . . . . . . . . . 154 Appendix C. M68HC05Cx Family Feature Comparisons MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 MOTOROLA Table of Contents Technical Data 13 Table of Contents ble Technical Data 14 MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 Table of Contents MOTOROLA Technical Data -- MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A List of Figures Figure 1-1 1-2 1-3 1-4 1-5 2-1 2-2 3-1 3-2 4-1 6-1 6-2 7-1 7-2 8-1 8-2 8-3 8-4 8-5 9-1 9-2 9-3 Title Page Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 40-Pin Dual In-Line Package . . . . . . . . . . . . . . . . . . . . . . . . . . 23 42-Pin Plastic Shrink Dual In-Line Package . . . . . . . . . . . . . . . 24 44-Lead Plastic Leaded Chip Carrier . . . . . . . . . . . . . . . . . . . . 25 44-Lead Quad Flat Pack. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Input/Output Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Stacking Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Interrupt Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Stop/Wait Mode Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Stop Recovery Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . .53 Port B Pullup Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 I/O Circuitry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Timer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Output Compare Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Input Capture Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Timer Control Register (TCR). . . . . . . . . . . . . . . . . . . . . . . . . . 65 Timer Status Register (TSR) . . . . . . . . . . . . . . . . . . . . . . . . . . 66 SCI Data Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 SCI Transmitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 SCI Receiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 MOTOROLA List of Figures Technical Data 15 List of Figures Figure 9-4 9-5 9-6 9-7 9-8 10-1 10-2 10-3 10-4 10-5 10-6 Title Page SCI Data Register (SCDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 SCI Control Register 1 (SCCR1) . . . . . . . . . . . . . . . . . . . . . . . 79 SCI Control Register 2 (SCCR2) . . . . . . . . . . . . . . . . . . . . . . . 80 SCI Status Register (SCSR). . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Baud Rate Register (BAUD) . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Data Clock Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Serial Peripheral Interface Block Diagram . . . . . . . . . . . . . . . . 91 Serial Peripheral Interface Master-Slave Interconnection . . . . 92 SPI Control Register (SPCR) . . . . . . . . . . . . . . . . . . . . . . . . . . 93 SPI Status Register (SPSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 SPI Data Register (SPSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 11-1 User Mode Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 11-2 Self-Check Circuit Schematic . . . . . . . . . . . . . . . . . . . . . . . . . 101 13-1 Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 13-2 Maximum Supply Current versus Internal Clock Frequency, VDD = 5.5 V . . . . . . . . . . . . . . . 127 13-3 Maximum Supply Current versus Internal Clock Frequency, VDD = 3.6 V . . . . . . . . . . . . . . . 127 13-4 TCAP Timing Relationships . . . . . . . . . . . . . . . . . . . . . . . . . . 129 13-5 External Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 13-6 External Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130 13-7 STOP Recovery Timing Diagram . . . . . . . . . . . . . . . . . . . . . . 131 13-8 Power-On Reset Timing Diagram. . . . . . . . . . . . . . . . . . . . . . 131 13-9 SPI Master Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 134 13-10 SPI Slave Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Technical Data 16 MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 List of Figures MOTOROLA Technical Data -- MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A List of Tables Table 4-1 7-1 9-1 9-2 9-3 Title Page Vector Addresses for Interrupts and Reset. . . . . . . . . . . . . . . . 42 I/O Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Baud Rate Generator Clock Prescaling . . . . . . . . . . . . . . . . . . 84 Baud Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Baud Rate Selection Examples . . . . . . . . . . . . . . . . . . . . . . . .86 10-1 Serial Peripheral Rate Selection. . . . . . . . . . . . . . . . . . . . . . . . 94 11-1 Operating Mode Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 11-2 Self-Check Circuit LED Codes . . . . . . . . . . . . . . . . . . . . . . . . 100 12-1 12-2 12-3 12-4 12-5 12-6 12-7 C-1 Register/Memory Instructions . . . . . . . . . . . . . . . . . . . . . . . . . 108 Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . . . .109 Jump and Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . . 111 Bit Manipulation Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . 112 Control Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 M68HC05Cx Feature Comparison . . . . . . . . . . . . . . . . . . . . . 156 MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 MOTOROLA List of Tables Technical Data 17 List of Tables Technical Data 18 MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 List of Tables MOTOROLA Technical Data -- MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A Section 1. General Description 1.1 Contents 1.2 1.3 1.4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Mask Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 1.5 Functional Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 1.5.1 VDD and VSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 1.5.2 IRQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 1.5.3 OSC1 and OSC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 1.5.4 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 1.5.5 TCAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 1.5.6 TCMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 1.5.7 Port A (PA0-PA7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 1.5.8 Port B (PB0-PB7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 1.5.9 Port C (PC0-PC7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 1.5.10 Port D (PD0-PD5 and PD7). . . . . . . . . . . . . . . . . . . . . . . . . 27 1.2 Introduction The MC68HC05C8A is an enhanced version of the MC68HC05C8. It includes keyboard scanning logic, a high current pin, a computer operating properly (COP) watchdog timer, and read-only memory (ROM) security feature. MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 MOTOROLA General Description Technical Data 19 General Description ption 1.3 Features * * * M68HC05 core Single 3.0- to 5.5-volt supply Available packages: - 40-pin dual in-line (DIP) - 42-pin plastic shrink dual in-line (SDIP) - 44-lead plastic leaded chip carrier (PLCC) - 44-lead quad flat pack (QFP) * * * * * * * * * * * * * * * * * On-chip oscillator for crystal/ceramic resonator Fully static operation 7744 bytes of user ROM ROM security feature 176 bytes of on-chip random-access memory (RAM) Asynchronous serial communications interface (SCI) system Synchronous serial peripheral interface (SPI) system 16-bit capture/compare timer system Computer operating properly (COP) watchdog timer 24 bidirectional input/output (I/O) lines Seven input-only lines User mode Self-check mode Power-saving stop and wait modes High current sink and source on one port pin (PC7) Mask selectable external interrupt sensitivity Mask-programmable keyscan logic Technical Data 20 MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 General Description MOTOROLA General Description Features PA0 DATA DIRECTION A USER ROM AND USER VECTORS -- 7744 BYTES PA1 PA2 PORT A PA3 PA4 PA5 PA6 PA7 SRAM -- 176 BYTES PB0* DATA DIRECTION B PB1* PB2* PORT B PB3* PB4* PB5* PB6* PB7* ACCUMULATOR INDEX REGISTER 0 0 0 0 0 0 0 0 1 1 STACK POINTER DATA DIRECTION C PC0 PC1 PC2 PORT C PC3 PC4 PC5 PC6 PC71/21/2 PD7 RDI(PD0) SCI BAUD RATE GENERATOR TDO(PD1) MISO(PD2) MOSI(PD3) POWER SPI SCK(PD4) SS(PD5) BAUD RATE GENERATOR TCMP TCAP SELF-CHECK ROM -- 240 BYTES IRQ RESET CPU CONTROL M68HC05 CPU CPU REGISTERS ALU PROGRAM COUNTER 1 1 1 H I N Z C CONDITION CODE REGISTER OSC2 OSC1 OSCILLATOR /2 INTERNAL PROCESSOR CLOCK PORT D COP SYSTEM V DD V SS 16-BIT CAPTURE/COMPARE TIMER SYSTEM * Port B pins also function as external interrupts. PC7 has a high current sink and source capability. Figure 1-1. Block Diagram MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 MOTOROLA General Description Technical Data 21 General Description 1.4 Mask Options Eight mask options are available to select the pullup/interrupts on port B on a pin-by-pin basis. There are also four mask options for: 1. IRQ (edge-sensitive only or edge- and level-sensitive) 2. CLOCK (crystal or RC) 3. COP (enable or disable) 4. STOP (enable or disable). 1.5 Functional Pin Description The MC68HC05C8A is available in a 40-pin DIP (see Figure 1-2), 42-pin SDIP (see Figure 1-3), 44-pin PLCC (see Figure 1-4), and 44-pin QFP (see Figure 1-5). The following paragraphs describe the general function of each pin. NOTE: A line over a signal name indicates an active low signal. For example, RESET is active high and RESET is active low. Any reference to voltage, current, resistance, capacitance, time, or frequency specified in the following paragraphs will refer to the nominal values. The exact values and their tolerance or limits are specified in Section 13. Electrical Specifications. Technical Data 22 MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 General Description MOTOROLA General Description Functional Pin Description RESET IRQ NC* PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VDD OSC1 OSC2 TCAP PD7 TCMP PD5/SS PD4/SCK PD3/MOSI PD2/MISO PD1/TDO PD0/RDI PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 * If MC68HC705C8A OTPs are to be used in the same application, this pin should be tied to VDD. Figure 1-2. 40-Pin Dual In-Line Package MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 MOTOROLA General Description Technical Data 23 General Description RESET IRQ NC* PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PB0 PB1 PB2 PB3 NC PB4 PB5 PB6 PB7 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 VDD OSC1 OSC2 TCAP PD7 TCMP PD5/SS PD4/SCK PD3/MOSI PD2/MISO PD1/TDO PD0/RDI PC0 PC1 PC2 NC PC3 PC4 PC5 PC6 PC7 * If MC68HC705C8A OTPs are to be used in the same application, this pin should be tied to VDD. Figure 1-3. 42-Pin Plastic Shrink Dual In-Line Package Technical Data 24 MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 General Description MOTOROLA General Description Functional Pin Description RESET OSC1 OSC2 43 42 TCAP 41 PA6 PA7 NC* VDD IRQ NC 1 44 40 39 38 37 36 35 34 33 32 31 30 29 6 5 4 3 2 NC PA5 PA4 PA3 PA2 PA1 PA0 PB0 PB1 PB2 PB3 PB4 7 8 9 10 11 12 13 14 15 16 17 20 21 22 23 24 25 26 27 18 19 28 PD7 TCMP PD5/SS PD4/SCK PD3/MOSI PD2/MISO PD1/TDO PD0/RDI PC0 PC1 PC2 NC PB5 PB6 PB7 NC PC7 PC6 PC5 PC0 PC4 PC1 * If MC68HC705C8A OTPs are to be used in the same application, this pin should be tied to VDD. Figure 1-4. 44-Lead Plastic Leaded Chip Carrier PD3/MOSI PD2/MISO PD4/SCK PD1/TDO PD5/SS PD0/RDI TCMP PC2 PC3 PC3 NC PC4 PC5 PC6 PC7 VSS NC PB7 PB6 PB5 PB4 21 20 19 18 17 16 15 14 13 PB3 PB2 PD7 TCAP OSC2 OSC1 VDD NC NC RESET IRQ NC* PA7 33 32 31 30 29 28 27 26 25 24 23 34 22 35 36 37 38 39 40 41 42 43 44 1 PA6 VSS 2 3 PA4 4 PA3 5 PA2 6 PA1 7 PA0 8 PB0 12 9 10 11 PB1 * If MC68HC705C8A OTPs are to be used in the same application, this pin should be tied to VDD. Figure 1-5. 44-Lead Quad Flat Pack MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 MOTOROLA General Description PA5 Technical Data 25 General Description 1.5.1 VDD and VSS Power is supplied to the microcontroller using these two pins. VDD is the positive supply and VSS is ground. 1.5.2 IRQ This pin has a mask selectable option that provides two different choices of interrupt triggering sensitivity. The IRQ pin contains an internal Schmitt trigger as part of its input to improve noise immunity. Refer to Section 4. Interrupts for more detail. 1.5.3 OSC1 and OSC2 These pins provide control input for an on-chip clock oscillator circuit. A crystal, a ceramic resonator, a resistor/capacitor combination, or an external signal connects to these pins providing a system clock. The internal bus rate is one-half the external oscillator frequency. 1.5.4 RESET This active low pin is used to reset the MCU to a known startup state by pulling RESET low. The RESET pin contains an internal Schmitt trigger as part of its input to improve noise immunity. 1.5.5 TCAP This pin controls the input capture feature for the on-chip programmable timer. The TCAP pin contains an internal Schmitt trigger as part of its input to improve noise immunity. 1.5.6 TCMP The TCMP pin provides an output for the output compare feature of the on-chip timer subsystem. Technical Data 26 MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 General Description MOTOROLA General Description Functional Pin Description 1.5.7 Port A (PA0-PA7) These eight input/output (I/O) lines comprise port A. The state of any pin is software programmable and all port A lines are configured as input during power-on or reset. For detailed information on I/O programming, see 7.7 Input/Output Programming. 1.5.8 Port B (PB0-PB7) These eight I/O lines comprise port B. The state of any pin is software programmable, and all port B lines are configured as input during poweron or reset. Port B has mask option enabled pullup devices and interrupt capability by pin. The interrupts and pullups are enabled together. For a detailed description on I/O programming, refer to 7.7 Input/Output Programming. 1.5.9 Port C (PC0-PC7) These eight I/O lines comprise port C. The state of any pin is software programmable and all port C lines are configured as input during poweron or reset. PC7 has high current sink and source capability. For a detailed description on I/O programming, refer to 7.7 Input/Output Programming. 1.5.10 Port D (PD0-PD5 and PD7) These seven port lines comprise port D. PD7 and PD5-PD0 are input only. PD0 and PD1 are shared with the SCI subsystem and PD2-PD5 are shared with the SPI subsystem. For a detailed description on I/O programming, refer to 7.7 Input/Output Programming. MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 MOTOROLA General Description Technical Data 27 General Description Technical Data 28 MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 General Description MOTOROLA Technical Data -- MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A L05C8A Section 2. Memory 2.1 Contents 2.2 2.3 2.4 2.5 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Read-Only Memory (ROM). . . . . . . . . . . . . . . . . . . . . . . . . . . .29 ROM Security Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Random-Access Memory (RAM) . . . . . . . . . . . . . . . . . . . . . . . 30 2.2 Introduction The MC68HC05C8A has an 8-Kbyte memory map, consisting of user read-only memory (ROM), user random-access memory (RAM), selfcheck ROM, and input/output (I/O) registers. See Figure 2-1 and Figure 2-2. 2.3 Read-Only Memory (ROM) The user ROM consists of 48 bytes of page zero ROM from $0020 to $004F, 7680 bytes of user ROM from $0100 to $1EFF, and 16 bytes of user vectors from $1FF0 to $1FFF. The self-check ROM and vectors are located from $1F00 to $1FEF. See Figure 2-1. Twelve of the user vectors, $1FF4-$1FFF, are dedicated to userdefined reset and interrupt vectors. The remaining four bytes from $1FF0-$1FF3 are not used. MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 MOTOROLA Memory Technical Data 29 Memory 2.4 ROM Security Feature A security(1) feature has been incorporated into the MC68HC05C8A to help prevent externally reading of code in the ROM. This feature aids in keeping customer developed software proprietary. 2.5 Random-Access Memory (RAM) The user RAM consists of 176 bytes and is used both for generalpurpose RAM and stack area. The stack begins at address $00FF. The stack pointer can access 64 bytes of RAM in the range $00FF to $00C0. See Figure 2-1. NOTE: Using the stack area for data storage or temporary work locations requires care to prevent it from being overwritten due to stacking from an interrupt or subroutine call. 1. No security feature is absolutely secure. However, Motorola's strategy is to make reading or copying the ROM difficult for unauthorized users. Technical Data 30 MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 Memory MOTOROLA Memory Random-Access Memory (RAM) $0000 I/O REGISTERS 32 BYTES $001F $0020 USER ROM 48 BYTES $004F $0050 RAM 176 BYTES $00BF $00C0 (STACK) 64 BYTES $00FF $0100 USER ROM 7680 BYTES PORT A DATA REGISTER PORT B DATA REGISTER PORT C DATA REGISTER PORT D DATA REGISTER PORT A DATA DIRECTION REGISTER PORT B DATA DIRECTION REGISTER PORT C DATA DIRECTION REGISTER UNUSED UNUSED UNUSED SPI CONTROL REGISTER SPI STATUS REGISTER SPI DATA REGISTER SCI BAUD RATE REGISTER SCI CONTROL REGISTER 1 SCI CONTROL REGISTER 2 SCI STATUS REGISTER SCI DATA REGISTER TIMER CONTROL REGISTER TIMER STATUS REGISTER INPUT CAPTURE REGISTER (HIGH) INPUT CAPTURE REGISTER (LOW) OUTPUT COMPARE REGISTER (HIGH) OUTPUT COMPARE REGISTER (LOW) TIMER COUNTER REGISTER (HIGH) TIMER COUNTER REGISTER (LOW) ALTERNATE COUNTER REGISTER (HIGH) ALTERNATE COUNTER REGISTER (LOW) UNUSED UNUSED UNUSED UNUSED $0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000A $000B $000C $000D $000E $000F $0010 $0011 $0012 $0013 $0014 $0015 $0016 $0017 $0018 $0019 $001A $001B $001C $001D $001E $001F COP REGISTER $1EFF $1F00 NOT USED (3 BYTES) SPI VECTOR (HIGH) SPI VECTOR (LOW) SCI VECTOR (HIGH) SCI VECTOR (LOW) TIMER VECTOR (HIGH) TIMER VECTOR (LOW) IRQ VECTOR (HIGH) IRQ VECTOR (LOW) SWI VECTOR (HIGH) SWI VECTOR (LOW) RESET VECTOR (HIGH BYTE) RESET VECTOR (LOW BYTE) SELF-CHECK ROM AND VECTORS 240 BYTES $1FEF $1FF0 $1FFF USER ROM VECTORS 16 BYTES $1FF0 $1FF1 $1FF2 $1FF3 $1FF4 $1FF5 $1FF6 $1FF7 $1FF8 $1FF9 $1FFA $1FFB $1FFC $1FFD $1FFE $1FFF Figure 2-1. Memory Map MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 MOTOROLA Memory Technical Data 31 Memory Addr. Register Name Read: Port A Data Register (PORTA) Write: See page 56. Reset: Read: Port B Data Register (PORTB) Write: See page 56. Reset: Read: Port C Data Register (PORTC) Write: See page 57. Reset: Read: Port D Data Register (PORTD) Write: See page 57. Reset: Bit 7 PA7 6 PA6 5 PA5 4 PA4 3 PA3 2 PA2 1 PA1 Bit 0 PA0 $0000 Unaffected by reset PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 $0001 Unaffected by reset PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 $0002 Unaffected by reset PD7 PD5 PD4 PD3 PD2 PD1 PD0 $0003 Unaffected by reset DDRA6 0 DDRB6 0 DDRA5 0 DDRB5 0 DDRC5 0 DDRA4 0 DDRB4 0 DDRC4 0 DDRA3 0 DDRB3 0 DDRC3 0 DDRA2 0 DDRB2 0 DDRC2 0 DDRA1 0 DDRB1 0 DDRC1 0 DDRA0 0 DDRB0 0 DDRC0 0 Read: Port A Data Direction Register DDRA7 $0004 (DDRA) Write: See page 56. Reset: 0 Read: Port B Data Direction Register DDRB7 $0005 (DDRB) Write: See page 56. Reset: 0 Read: Port C Data Direction Register DDRC7 DDRC6 $0006 (DDRC) Write: See page 57. Reset: 0 0 $0007 Unimplemented $0008 Unimplemented $0009 Unimplemented = Unimplemented R = Reserved U = Unaffected Figure 2-2. Input/Output Registers (Sheet 1 of 4) Technical Data 32 MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 Memory MOTOROLA Memory Random-Access Memory (RAM) Addr. Register Name Read: SPI Control Register (SPCR) Write: See page 93. Reset: Read: SPI Status Register (SPSR) Write: See page 94. Reset: Bit 7 SPIE 0 SPIF 0 6 SPE 0 WCOL 0 SPD6 5 4 MSTR 3 CPOL 0 0 2 CPHA 0 0 1 SPR1 U 0 Bit 0 SPR0 U 0 $000A 0 0 0 MODF $000B 0 SPD5 0 SPD4 0 SPD31 0 SPD2 U SPD1 U SPD0 $000C Read: SPI Data Register SPD7 (SPDR) Write: See page 96. Reset: Read: SCI Baud Rate Register BAUD Write: See page 84. Reset: Read: SCI Control Register 1 (SCCR1) Write: See page 79. Reset: Read: SCI Control Register 2 (SCCR2) Write: See page 80. Reset: 0 0 R8 Unaffected by reset 0 0 T8 SCP1 0 0 SCP0 0 M 0 0 WAKE SCR2 U 0 SCR1 U 0 SCR0 U 0 $000D $000E Unaffected by reset TIE 0 TCIE 0 TC RIE 0 RDRF ILIE 0 IDLE TE 0 OR RE 0 NF RMW 0 FE 0 0 SDC5 0 SCD5 0 SCD4 0 SCD3 0 SCD2 0 SCD1 0 SCD0 SBK 0 $000F $0010 Read: TDRE SCI Status Register (SCSR) Write: See page 82. Reset: 0 Read: SCI Data Register SCD7 (SCDAT) Write: See page 78. Reset: Read: Timer Control Register (TCR) Write: See page 65. Reset: ICIE 0 $0011 Unaffected by reset OCIE 0 TOIE 0 0 0 R 0 0 = Reserved 0 0 IEDGE U OLVL 0 $0012 = Unimplemented U = Unaffected Figure 2-2. Input/Output Registers (Sheet 2 of 4) MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 MOTOROLA Memory Technical Data 33 Memory Addr. Register Name Read: Timer Status Register (TSR) Write: See page 66. Reset: Bit 7 ICF 6 OCF 5 TOF 4 0 3 0 2 0 1 0 Bit 0 0 $0013 U U Bit 14 U Bit 13 0 Bit 12 0 Bit 11 0 Bit 10 0 Bit 9 0 Bit 8 $0014 Read: Bit 15 Input Capture Register High (ICR) Write: See page 63. Reset: Read: Input Capture Register Low (ICR) Write: See page 63. Reset: Bit 7 Unaffected by reset Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 $0015 Unaffected by reset Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 $0016 Read: Output Compare Register Bit 15 High (OCR) Write: See page 62. Reset: Read: Output Compare Register Low (OCR) Write: See page 62. Reset: Bit 7 Unaffected by reset Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 $0017 Unaffected by reset Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 $0018 Read: Bit 15 Timer Counter Register High (TCNT) Write: See page 61. Reset: 1 Timer Counter Register Low Read: (TCNT) Write: See page 61. Reset: Bit 7 1 Bit 6 1 Bit 5 1 Bit 4 1 Bit 3 1 Bit 2 1 Bit 1 1 Bit 0 $0019 1 1 Bit 14 1 Bit 13 1 Bit 12 1 Bit 11 1 Bit 10 1 Bit 9 1 Bit 8 $001A Read: Bit 15 Alternate Counter Register High (ALTCNT) Write: See page 61. Reset: 1 Read: Alternate Counter Register Low (ALTCNT) Write: See page 61. Reset: Bit 7 1 Bit 6 1 Bit 5 1 Bit 4 1 Bit 3 1 Bit 2 1 Bit 1 1 Bit 0 $001B 1 1 1 1 R 1 = Reserved 1 1 1 = Unimplemented U = Unaffected Figure 2-2. Input/Output Registers (Sheet 3 of 4) Technical Data 34 MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 Memory MOTOROLA Memory Random-Access Memory (RAM) Addr. $001C Register Name Unimplemented Bit 7 6 5 4 3 2 1 Bit 0 $001D Unimplemented $001E Unimplemented $001F Reserved R R R R R R R R Read: $1FF0 COP Reset Register Write: See page 48. Reset: User ROM data COPC 0 0 0 0 R 0 = Reserved 0 0 0 = Unimplemented U = Unaffected Figure 2-2. Input/Output Registers (Sheet 4 of 4) MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 MOTOROLA Memory Technical Data 35 Memory Technical Data 36 MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 Memory MOTOROLA Technical Data -- MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A Section 3. Central Processor Unit (CPU) 3.1 Contents 3.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.3 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.3.1 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.3.2 Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.3.3 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.3.4 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.3.5 Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.2 Introduction This section describes the central processor unit (CPU) registers. 3.3 CPU Registers The five CPU registers are shown in Figure 3-1 and the interrupt stacking order in Figure 3-2. MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 MOTOROLA Central Processor Unit (CPU) Technical Data 37 Central Processor Unit (CPU) 7 7 A 0 0 ACCUMULATOR X 12 PC 12 0 0 0 0 0 7 1 1 SP CCR H I N Z C 0 0 INDEX REGISTER PROGRAM COUNTER STACK POINTER CONDITION CODE REGISTER Figure 3-1. Programming Model 7 1 INCREASING MEMORY ADDRESSES R E T U R N 1 1 0 CONDITION CODE REGISTER ACCUMULATOR INDEX REGISTER PCH PCL STACK I N T E R R U P T DECREASING MEMORY ADDRESSES UNSTACK NOTE: Since the stack pointer decrements during pushes, the PCL is stacked first, followed by PCH, etc. Pulling from the stack is in the reverse order. Figure 3-2. Stacking Order 3.3.1 Accumulator The accumulator (A) shown in Figure 3-1 is a general-purpose 8-bit register used to hold operands and results of arithmetic calculations or data manipulations. 3.3.2 Index Register The index register (X) is an 8-bit register used by the indexed addressing X) value to create an effective address. The index register also may be used as a temporary storage area. Technical Data 38 MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 Central Processor Unit (CPU) MOTOROLA Central Processor Unit (CPU) CPU Registers 3.3.3 Program Counter The program counter (PC) is a 13-bit register that contains the address of the next byte to be fetched. 3.3.4 Stack Pointer The stack pointer (SP) contains the address of the next free location on the stack. During an MCU reset or the reset stack pointer (RSP) instruction, the stack pointer is set to location $00FF. The stack pointer is then decremented as data is pushed onto the stack and incremented as data is pulled from the stack. When accessing memory, the seven most significant bits (MSB) are permanently set to 0000011. These eight bits are appended to the six least significant register bits (LSB) to produce an address within the range of $00FF to $00C0. Subroutines and interrupts may use up to 64 (decimal) locations. If 64 locations are exceeded, the stack pointer wraps around and loses the previously stored information. A subroutine call occupies two locations on the stack; an interrupt uses five locations. 3.3.5 Condition Code Register The condition code register (CCR) is a 5-bit register in which four bits are used to indicate the results of the instruction just executed, and the fifth bit indicates whether interrupts are masked. These bits can be tested individually by a program, and specific actions can be taken as a result of their state. Each bit is explained here. H -- Half Carry This bit is set during ADD and ADC operations to indicate that a carry occurred between bits 3 and 4. I -- Interrupt When this bit is set, the timer and external interrupt are masked (disabled). If an interrupt occurs while this bit is set, the interrupt is latched and processed as soon as the interrupt bit is cleared. MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 MOTOROLA Central Processor Unit (CPU) Technical Data 39 Central Processor Unit (CPU) N -- Negative When set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was negative. Z -- Zero When set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was 0. C -- Carry/Borrow When set, this bit indicates that a carry or borrow out of the arithmetic logical unit (ALU) occurred during the last arithmetic operation. This bit also is affected during bit test and branch instructions and during shifts and rotates. Technical Data 40 MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 Central Processor Unit (CPU) MOTOROLA Technical Data -- MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A L05C8A Section 4. Interrupts 4.1 Contents 4.2 4.3 4.4 4.5 4.6 4.7 4.8 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Hardware Controlled Interrupt Sequence . . . . . . . . . . . . . . . . . 43 Software Interrupt (SWI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 External Interrupt (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Timer Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Serial Communications Interrupt (SCI) . . . . . . . . . . . . . . . . . . . 45 Serial Peripheral Interrupt (SPI) . . . . . . . . . . . . . . . . . . . . . . . .46 4.2 Introduction The microcontroller unit (MCU) can be interrupted five different ways: * Four maskable hardware interrupts, IRQ (interrupt request), SPI (serial peripheral interface), SCI (serial communications interface), and timer Non-maskable software interrupt instruction (SWI) * Port B interrupts, if enabled, are combined with the IRQ to form a single interrupt source. Interrupts cause the processor to save register contents on the stack and to set the interrupt mask (I bit) to prevent additional interrupts. The RTI (return to interrupt) instruction causes the register contents to be recovered from the stack and normal processing to resume. MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 MOTOROLA Interrupts Technical Data 41 Interrupts Unlike reset, hardware interrupts do not cause the current instruction execution to be halted, but they are considered pending until the current instruction is complete. NOTE: The current instruction is the one already fetched and being operated on. When the current instruction is complete, the processor checks all pending hardware interrupts. If interrupts are not masked (CCR I bit clear) and if the corresponding interrupt enable bit is set, the processor proceeds with interrupt processing; otherwise, the next instruction is fetched and executed. If both an external interrupt and a timer interrupt are pending at the end of an instruction execution, the external interrupt is serviced first. The SWI is executed the same as any other instruction, regardless of the Ibit state. Vector addresses for all interrupts, including reset, are listed in Table 4-1. Table 4-1. Vector Addresses for Interrupts and Reset Register Flag Name N/A N/A N/A TSR TSR TSR SCSR SCSR SCSR SCSR SCSR SPSR SPSR N/A N/A N/A ICF OCF TOF TDRE TC RDRF IDLE OR SPIF MODF Interrupts Reset Software External interrupt Timer input capture Timer output compare Timer overflow Transmit buffer empty Transmit complete Receiver buffer full Idle line detect Overrun Transfer complete Mode fault CPU Interrupt Vector Address RESET SWI IRQ TIMER TIMER TIMER SCI SCI SCI SCI SCI SPI SPI $1FFE-$1FFF $1FFC-$1FFD $1FFA-$1FFB $1FF8-$1FF9 $1FF8-$1FF9 $1FF8-$1FF9 $1FF6-$1FF7 $1FF6-$1FF7 $1FF6-$1FF7 $1FF6-$1FF7 $1FF6-$1FF7 $1FF4-$1FF5 $1FF4-$1FF5 Technical Data 42 MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 Interrupts MOTOROLA Interrupts Hardware Controlled Interrupt Sequence 4.3 Hardware Controlled Interrupt Sequence Three functions (RESET, STOP, and WAIT) are not in the strictest sense interrupts; however, they are acted upon in a similar manner. Flowcharts for hardware interrupts are shown in Figure 4-1. 1. RESET -- A low input on the RESET input pin causes the program to vector to its starting address, which is specified by the contents of memory locations $1FFE and $1FFF. The I bit in the condition code register is also set. Much of the MCU is configured to a known state during this type of reset, as previously described in Section 5. Resets. 2. STOP -- The STOP instruction causes the oscillator to be turned off and the processor to "sleep" until an external interrupt (IRQ) or reset occurs. 3. WAIT -- The WAIT instruction causes all processor clocks to stop, but leaves the timer clock running. This "rest" state of the processor can be cleared by reset, an external interrupt (IRQ), serial peripheral interface, serial communications interface, or timer interrupt. These individual interrupts have no special wait vectors. 4.4 Software Interrupt (SWI) ) The software interrupt (SWI) is an executable instruction and a nonmaskable interrupt. It is executed regardless of the state of the I bit in the CCR. If the I bit is 0 (interrupts enabled), SWI executes after interrupts which were pending when the SWI was fetched but before interrupts generated after the SWI was fetched. The interrupt service routine address is specified by the contents of memory locations $1FFC and $1FFD. MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 MOTOROLA Interrupts Technical Data 43 Interrupts FROM RESET Y I BIT IN CCR SET? N IRQ EXTERNAL INTERRUPT ? N INTERNAL TIMER INTERRUPT ? N INTERNAL SCI INTERRUPT ? N INTERNAL SPI INTERRUPT ? N FETCH NEXT INSTRUCTION Y Y CLEAR IRQ REQUEST LATCH Y Y STACK PC, X, A, CCR SET I BIT IN CC REGISTER SWI INSTRUCTION ? N Y RTI INSTRUCTION ? N RESTORE REGISTERS FROM STACK: CCR, A, X, PC EXECUTE INSTRUCTION Y LOAD PC FROM: SWI: $1FFC-$1FFD IRQ: $1FFA-$1FFB TIMER: $1FF8-$1FF9 SCI: $1FF6-$1FF7 Figure 4-1. Interrupt Flowchart Technical Data 44 MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 Interrupts MOTOROLA Interrupts External Interrupt (IRQ) 4.5 External Interrupt (IRQ) If the interrupt mask bit (I bit) of the CCR is set, all maskable interrupts (internal and external) are disabled. Clearing the I bit enables interrupts. The interrupt request is latched immediately following the falling edge of IRQ. It is then synchronized internally and serviced as specified by the contents of $1FFA and $1FFB. When any of the port B pullups are enabled, that pin becomes an additional external interrupt source which is coupled to the IRQ pin logic. It follows the same edge/edge-level selection that the IRQ pin has. See Figure 7-1 . Port B Pullup Option. Either a level-sensitive and edge-sensitive trigger, or an edge-sensitiveonly trigger operation is selectable by mask option. NOTE: The internal interrupt latch is cleared in the first part of the interrupt service routine; therefore, one external interrupt pulse could be latched and serviced as soon as the I bit is cleared. 4.6 Timer Interrupt Three different timer interrupt flags cause a timer interrupt whenever they are set and enabled. The interrupt flags are in the timer status register (TSR), and the enable bits are in the timer control register (TCR). Any of these interrupts will vector to the same interrupt service routine, located at the address specified by the contents of memory locations $1FF8 and $1FF9. 4.7 Serial Communications Interrupt (SCI) Five different SCI interrupt flags cause an SCI interrupt whenever they are set and enabled. The interrupt flags are in the SCI status register (SCSR), and the enable bits are in the SCI control register 2 (SCCR2). Any of these interrupts will vector to the same interrupt service routine, located at the address specified by the contents of memory locations $1FF6 and $1FF7. MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 MOTOROLA Interrupts Technical Data 45 Interrupts 4.8 Serial Peripheral Interrupt (SPI) Two different SPI interrupt flags cause an SPI interrupt whenever they are set and enabled. The interrupt flags are in the SPI status register (SPSR), and the enable bits are in the SPI control register (SPCR). Either of these interrupts will vector to the same interrupt service routine, located at the address specified by the contents of memory locations $1FF4 and $1FF5. Technical Data 46 MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 Interrupts MOTOROLA Technical Data -- MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A 05C8A Section 5. Resets 5.1 Contents 5.2 5.3 5.4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Power-On Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 RESET Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 5.5 Computer Operating Properly (COP) Reset . . . . . . . . . . . . . . . 48 5.5.1 Resetting the COP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 5.5.2 COP During Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 5.5.3 COP During Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 5.5.4 COP During Self-Check Mode . . . . . . . . . . . . . . . . . . . . . . . 49 5.2 Introduction The microcontroller unit (MCU) can be reset three ways: 1. Initial power-on reset function 2. Active low input to the RESET pin 3. Computer operating properly (COP) reset MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 MOTOROLA Resets Technical Data 47 Resets 5.3 Power-On Reset (POR) An internal reset is generated on power-up to allow the internal clock generator to stabilize. The power-on reset is strictly for power turn-on conditions and should not be used to detect a drop in the power supply voltage. There is a 4064 internal processor clock cycle (tCYC) oscillator stabilization delay after the oscillator becomes active. If the RESET pin is low after the end of this 4064-cycle delay, the MCU will remain in the reset condition until RESET goes high. For additional information, refer to Figure 13-8. Power-On Reset Timing Diagram. 5.4 RESET Pin T The MCU is reset when a logic 0 is applied to the RESET input for a period of one and one-half machine cycles (tRL). 5.5 Computer Operating Properly (COP) Reset This device includes a watchdog COP feature as a mask option. The COP is implemented with an 18-bit ripple counter. This provides a timeout period of 64 milliseconds at a bus rate of 2 MHz. If the COP should time out, a system reset will occur and the device will be re-initialized in the same fashion as a power-on reset (POR) or external reset. 5.5.1 Resetting the COP Preventing a COP reset is done by writing a logic 0 to the COPC bit. This action will reset the counter and begin the timeout period again. The COPC bit is bit 0 of address $1FF0. A read of address $1FF0 will result in the user defined ROM data at that location. Technical Data 48 MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 Resets MOTOROLA Resets Computer Operating Properly (COP) Reset 5.5.2 COP During Wait Mode The COP will continue to operate normally during wait mode. The software should pull the device out of wait mode periodically and reset the COP by writing to the COPC bit to prevent a COP reset. 5.5.3 COP During Stop Mode Stop mode disables the oscillator circuit and thereby turns the clock off for the entire device. The COP counter will be reset when stop mode is entered. If a reset is used to exit stop mode, the COP counter will be reset after the 4064 cycles of delay after stop mode. If an interrupt is used to exit stop mode, the COP counter will not be reset after the 4064-cycle delay and will have that many cycles already counted when control is returned to the program. 5.5.4 COP During Self-Check Mode The COP is disabled by hardware during self-check mode. MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 MOTOROLA Resets Technical Data 49 Resets Technical Data 50 MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 Resets MOTOROLA Technical Data -- MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A L05C8A Section 6. Low-Power Modes 6.1 Contents 6.2 6.3 6.4 6.5 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Stop Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.2 Introduction This section describes the two low-power modes -- stop and wait. Figure 6-1 shows the sequence of events caused by the STOP and WAIT instructions. MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 MOTOROLA Low-Power Modes Technical Data 51 Low-Power Modes STOP WAIT STOP OSCILLATOR AND ALL CLOCKS CLEAR I BIT OSCILLATOR ACTIVE TIMER CLOCK ACTIVE PROCESSOR CLOCKS STOPPED CLEAR I BIT N RESET RESET N N EXTERNAL INTERRUPT (IRQ) Y Y Y EXTERNAL INTERRUPT (IRQ) Y Y N TIMER INTERRUPT TURN ON OSCILLATOR WAIT FOR TIME DELAY TO STABILIZE RESTART PROCESSOR CLOCK Y N SCI INTERRUPT 1. FETCH RESET VECTOR OR 2. SERVICE INTERRUPT A. STACK B. SET I BIT C. VECTOR TO INTERRUPT ROUTINE 1. FETCH RESET VECTOR OR 2. SERVICE INTERRUPT A. STACK B. SET I BIT C. VECTOR TO INTERRUPT ROUTINE N SPI INTERRUPT N Figure 6-1. Stop/Wait Mode Flowchart 6.3 Stop Mode The STOP instruction places the microcontroller unit (MCU) in its lowestpower consumption mode. In stop mode, the internal oscillator is turned off, halting all internal processing, including timer operation. During stop mode, the TCR bits are altered to remove any pending timer interrupt request and to disable any further timer interrupts. The timer prescaler is cleared. The I bit in the condition code register is cleared to enable external interrupts. All other registers and memory remain Technical Data 52 MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 Low-Power Modes MOTOROLA Low-Power Modes Stop Recovery unaltered. All input/output lines remain unchanged. The processor can be brought out of stop mode only by an external interrupt or reset. 6.4 Stop Recovery The processor can be brought out of stop mode only by an external interrupt or reset. See Figure 6-2. 6.5 Wait Mode The WAIT instruction places the MCU in a low-power consumption mode, but the wait mode consumes more power than the stop mode. All CPU action is suspended, but the timer, serial communications interface (SCI), serial peripheral interface (SPI), and the oscillator remain active. Any interrupt or reset will cause the MCU to exit wait mode. During wait mode, the I bit in the CCR is cleared to enable interrupts. All other registers, memory, and input/output lines remain in their previous state. The timer may be enabled to allow a periodic exit from wait mode. OSC1 (1) tRL RESET t ILIH IRQ(2) (3) t ILCH 4064 tcyc IRQ INTERNAL CLOCK INTERNAL ADDRESS BUS Notes: 1. Represents the internal gating of the OSC1 pin 2. IRQ pin edge-sensitive option 3. IRQ pin level and edge sensitive option 1FFE 1FFE 1FFE 1FFE 1FFF RESET ($1FFE, $1FFF) OR INTERRUPT ($1FFA, $1FFB) VECTOR FETCH Figure 6-2. Stop Recovery Timing Diagram MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 MOTOROLA Low-Power Modes Technical Data 53 Low-Power Modes Technical Data 54 MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 Low-Power Modes MOTOROLA Technical Data -- MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A Section 7. Input/Output (I/O) Ports 7.1 Contents 7.2 7.3 7.4 7.5 7.6 7.7 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Input/Output Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 7.2 Introduction The MC68HC05C8A has three 8-bit input/output (I/O) ports.These 24 port pins are programmable as either inputs or outputs under software control of the data direction registers. Port D does not have a data direction register, and its seven pins are input only with the exception of certain serial communications (SCI)/serial peripheral interface (SPI) functions. NOTE: To avoid a glitch on the output pins, write data to the I/O port data register before writing a 1 to the corresponding data direction register. MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 MOTOROLA Input/Output (I/O) Ports Technical Data 55 Input/Output (I/O) Ports put/Output 7.3 Port A Port A is an 8-bit bidirectional port which does not share any of its pins with other subsystems. The port A data register is at $0000 and the data direction register (DDR) is at $0004. Reset does not affect the data registers, but clears the data direction registers, thereby returning the ports to inputs. Writing a 1 to a DDR bit sets the corresponding port bit to output mode. 7.4 Port B Port B is an 8-bit bidirectional port. The port B data register is at $0001 and the data direction register (DDR) is at $0005. Reset does not affect the data registers, but clears the data direction registers, thereby returning the ports to inputs. Writing a 1 to a DDR bit sets the corresponding port pin to output mode. Each of the port B pins has a mask programmable interrupt capability. This interrupt option also enables a pullup device when the pin is configured as an input (see Figure 7-1). The edge or edge and level sensitivity of the IRQ pin also will pertain to the enabled port B pins via mask options. Be careful when using port B pins that have the pullup enabled. Before switching from an output to an input, the data should be preconditioned to a 1 to prevent an interrupt from occurring. VDD VDD MASK OPTION DDR BIT IRQ SCHMITT TRIGGER PB0 NORMAL PORT CIRCUITRY AS SHOWN IN FIGURE 7-2 TO INTERRUPT LOGIC FROM ALL OTHER PORT B PINS Figure 7-1. Port B Pullup Option Technical Data 56 MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 Input/Output (I/O) Ports MOTOROLA Input/Output (I/O) Ports Port C 7.5 Port C Port C is an 8-bit bidirectional port. The port C data register is at $0002 and the data direction register (DDR) is at $0006. Reset does not affect the data registers, but clears the data direction registers, thereby returning the ports to inputs. Writing a 1 to a DDR bit sets the corresponding port bit to output mode. PC7 has a high current sink and source capability. 7.6 Port D Port D is a 7-bit fixed input port. Four of its pins are shared with the SPI subsystem, two more are shared with the SCI subsystem. Reset does not affect the data registers. During reset, all seven bits become valid input ports because all special function output drivers associated with the SCI, timer, and SPI subsystems are disabled. 7.7 Input/Output Programming I/O port pins may be programmed as inputs or outputs under software control. The direction of the pins is determined by the state of the corresponding bit in the port data direction register (DDR). Each I/O port has an associated DDR. Any I/O port pin is configured as an output if its corresponding DDR bit is set to a logic 1. A pin is configured as an input if its corresponding DDR bit is cleared to a logic 0. At power-on or reset, all DDRs are cleared, which configures all I/O pins as inputs. The data direction registers are capable of being written to or read by the processor. During the programmed output state, a read of the data register actually reads the value of the output data latch and not the I/O pin. For further information, refer to Table 7-1 and Figure 7-2. MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 MOTOROLA Input/Output (I/O) Ports Technical Data 57 Input/Output (I/O) Ports Table 7-1. I/O Pin Functions R/W(1) 0 0 1 1 DDR 0 1 0 1 I/O Pin Function The I/O pin is in input mode. Data is written into the output data latch. Data is written into the output data latch and output to the I/O pin. The state of the I/O pin is read. The I/O pin is in an output mode. The output data latch is read. 1. R/W is an internal signal. READ DDRx WRITE DDRx INTERNAL DATA BUS RESET WRITE PORTx DATA DIRECTION REGISTER x BIT PORT x DATA REGISTER BIT (LATCHED OUTPUT) [3] READ PORTx [1] I/O PIN [2] [1] This output buffer enables the latched output to drive the pin when DDR bit is 1 (output mode). [2] This input buffer is enabled when DDR bit is 0 (input mode). [3] This input buffer is enabled when DDR bit is 1 (output mode). Figure 7-2. I/O Circuitry Technical Data 58 MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 Input/Output (I/O) Ports MOTOROLA Technical Data -- MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A HC05C8A Section 8. Timer 8.1 Contents 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Output Compare Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Input Capture Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 Timer Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 Timer Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Timer During Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Timer During Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 8.2 Introduction The timer consists of a 16-bit, software-programmable counter driven by a fixed divide-by-four prescaler. This timer can be used for many purposes, including input waveform measurements while simultaneously generating an output waveform. Pulse widths can vary from several microseconds to many seconds. Refer to Figure 8-1 for a timer block diagram. Because the timer has a 16-bit architecture, each specific functional segment (capability) is represented by two registers. These registers contain the high and low byte of that functional segment. Generally, accessing the low byte of a specific timer function allows full control of that function; however, an access of the high byte inhibits that specific timer function until the low byte is also accessed. MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 MOTOROLA Timer Technical Data 59 Timer NOTE: The I bit in the condition code register should be set while manipulating both the high and low byte register of a specific timer function to ensure that an interrupt does not occur. INTERNAL BUS HIGH BYTE LOW BYTE INTERNAL PROCESSOR CLOCK 8-BIT BUFFER /4 $16 $17 OUTPUT COMPARE REGISTER HIGH BYTE 16-BIT FREE RUNNING COUNTER LOW BYTE $18 $19 HIGH BYTE LOW BYTE INPUT CAPTURE REGISTER $14 $15 COUNTER ALTERNATE REGISTER $1A $1B OUTPUT COMPARE CIRCUIT OVERFLOW DETECT CIRCUIT EDGE DETECT CIRCUIT D CLK TIMER ICF STATUS REGISTER OCF TOF $13 OUTPUT LEVEL REGISTER TIMER CONTROL REGISTER $12 Q C RESET ICIE OCIE TOIE IEDG OLVL INTERRUPT CIRCUIT OUTPUT LEVEL (TCMP) EDGE INPUT (TCAP) Figure 8-1. Timer Block Diagram Technical Data 60 MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 Timer MOTOROLA Timer Counter 8.3 Counter The key element in the programmable timer is a 16-bit, free-running counter or counter register, preceded by a prescaler that divides the internal processor clock by four. The prescaler gives the timer a resolution of 2.0 microseconds if the internal bus clock is 2.0 MHz. The counter is incremented during the low portion of the internal bus clock. Software can read the counter at any time without affecting its value. The double-byte, free-running counter can be read from either of two locations, $18, $19 (counter register) or $1A, $1B (counter alternate register). A read from only the least significant byte (LSB) of the freerunning counter ($19, $1B) receives the count value at the time of the read. If a read of the free-running counter or counter alternate register first addresses the most significant byte (MSB) ($18, $1A), the LSB ($19, $1B) is transferred to a buffer. This buffer value remains fixed after the first MSB read, even if the user reads the MSB several times. This buffer is accessed when reading the free-running counter or counter alternate register LSB ($19 or $1B) and, thus, completes a read sequence of the total counter value. In reading either the free-running counter or counter alternate register, if the MSB is read, the LSB must also be read to complete the sequence. The counter alternate register differs from the counter register in one respect: A read of the counter register MSB can clear the timer overflow flag (TOF). Therefore, the counter alternate register can be read at any time without the possibility of missing timer overflow interrupts due to clearing of the TOF. The free-running counter is configured to $FFFC during reset and is always a read-only register. During a power-on reset, the counter is also preset to $FFFC and begins running after the oscillator start-up delay. Because the free-running counter is 16 bits preceded by a fixed divideby-four prescaler, the value in the free-running counter repeats every 262,144 internal bus clock cycles. When the counter rolls over from $FFFF to $0000, the TOF bit is set. An interrupt can also be enabled whenever counter rollover occurs by setting its interrupt enable bit (TOIE). MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 MOTOROLA Timer Technical Data 61 Timer 8.4 Output Compare Register The 16-bit output compare register is made up of two 8-bit registers at locations $16 (MSB) and $17 (LSB). The output compare register is used for several purposes, such as indicating when a period of time has elapsed. All bits are readable and writable and are not altered by the timer hardware or reset. If the compare function is not needed, the two bytes of the output compare register can be used as storage locations. The output compare register contents are compared with the contents of the free-running counter continually, and if a match is found, the corresponding output compare flag (OCF) bit is set and the corresponding output level (OLVL) bit is clocked to an output level register. The output compare register values and the output level bit should be changed after each successful comparison to establish a new elapsed timeout. An interrupt also can accompany a successful output compare, provided the corresponding interrupt enable bit (OCIE) is set. After a processor write cycle to the output compare register containing the MSB ($16), the output compare function is inhibited until the LSB ($17) is written also. The user must write both bytes (locations) if the MSB is written first. A write made only to the LSB ($17) will not inhibit the compare function. The free-running counter is updated every four internal bus clock cycles. The minimum time required to update the output compare register is a function of the program rather than the internal hardware. The processor can write to either byte of the output compare register without affecting the other byte. The output level (OLVL) bit is clocked to the output level register regardless of whether the output compare flag (OCF) is set or clear. Figure 8-2 shows the logic of the output compare function. Technical Data 62 MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 Timer MOTOROLA Timer Input Capture Register 15 COUNTER HIGH BYTE COUNTER LOW BYTE 0 16-BIT COMPARATOR 15 87 0 PIN CONTROL LOGIC TCMP OUTPUT COMPARE REGISTER HIGH OUTPUT COMPARE REGISTER LOW TIMER INTERRUPT REQUEST ICIE OCIE TOIE ICF OCF $0012 TOF $0013 TIMER CONTROL REGISTER TIMER STATUS REGISTER Figure 8-2. Output Compare Operation 8.5 Input Capture Register Two 8-bit registers, which make up the 16-bit input capture register, are read-only and are used to latch the value of the free-running counter after the corresponding input capture edge detector senses a defined transition. The level transition which triggers the counter transfer is defined by the corresponding input edge bit (IEDG). Reset does not affect the contents of the input capture register except when exiting stop mode. The result obtained by an input capture will be one more than the value of the free-running counter on the rising edge of the internal bus clock preceding the external transition. This delay is required for internal synchronization. Resolution is one count of the free-running counter, which is four internal bus clock cycles. The free-running counter contents are transferred to the input capture register on each proper signal transition regardless of whether the input capture flag (ICF) is set or clear. The input capture register always contains the free-running counter value that corresponds to the most recent input capture. MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 MOTOROLA Timer Technical Data 63 Timer After a read of the input capture register ($14) MSB, the counter transfer is inhibited until the LSB ($15) is also read. This characteristic causes the time used in the input capture software routine and its interaction with the main program to determine the minimum pulse period. A read of the input capture register LSB ($15) does not inhibit the freerunning counter transfer, since they occur on opposite edges of the internal bus clock. Figure 8-3 shows the logic of the input capture function. 15 $0018 TIMER REGISTER HIGH 87 $0019 TIMER REGISTER LOW 0 TCMP EDGE SELECT/DETECT LOGIC LATCH 15 87 INPUT CAPTURE REGISTER LOW $0015 0 INPUT CAPTURE REGISTER HIGH $0014 TIMER INTERRUPT REQUEST ICIE OCIE TOIE OCF TOF TIMER STATUS REGISTER $0013 ICF IEDG $0012 TIMER CONTROL REGISTER Figure 8-3. Input Capture Operation Technical Data 64 MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 Timer MOTOROLA Timer Timer Control Register 8.6 Timer Control Register l The timer control register (TCR) is a read/write register containing five control bits. Three bits control interrupts associated with the timer status register flags ICF, OCF, and TOF. Address: $0012 Bit 7 Read: Write: Reset: ICIE 0 U = Unaffected 6 OCIE 0 5 TOIE 0 4 0 0 3 0 0 2 0 0 1 IEDG U Bit 0 OLVL 0 Figure 8-4. Timer Control Register (TCR) ICIE -- Input Capture Interrupt Enable Bit 1 = Interrupt enabled 0 = Interrupt disabled OCIE -- Output Compare Interrupt Enable Bit 1 = Interrupt enabled 0 = Interrupt disabled TOIE -- Timer Overflow Interrupt Enable Bit 1 = Interrupt enabled 0 = Interrupt disabled IEDG -- Input Edge Bit Value of input edge determines which level transition on TCAP pin will trigger free-running counter transfer to the input capture register. 1 = Positive edge 0 = Negative edge Reset does not affect the IEDG bit. OLVL -- Output Level Bit Value of output level is clocked into output level register by the next successful output compare and will appear on the TCMP pin. 1 = High output 0 = Low output MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 MOTOROLA Timer Technical Data 65 Timer Bits 2, 3, and 4 -- Not used Always read 0 8.7 Timer Status Register The timer status register (TSR) is a read-only register containing three status flag bits. Address: $0013 Bit 7 Read: Write: Reset: U U U 0 U = Unaffected 0 0 0 0 ICF 6 OCF 5 TOF 4 0 3 0 2 0 1 0 Bit 0 0 = Unimplemented Figure 8-5. Timer Status Register (TSR) ICF -- Input Capture Flag 1 = Flag set when selected polarity edge is sensed by input capture edge detector 0 = Flag cleared when TSR and input capture low register ($15) are accessed OCF -- Output Compare Flag 1 = Flag set when output compare register contents match the freerunning counter contents 0 = Flag cleared when TSR and output compare low register ($17) are accessed TOF -- Timer Overflow Flag 1 = Flag set when free-running counter transition from $FFFF to $0000 occurs 0 = Flag cleared when TSR and counter low register ($19) are accessed Bits 0-4 -- Not used Always read 0 Technical Data 66 MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 Timer MOTOROLA Timer Timer During Wait Mode Accessing the timer status register satisfies the first condition required to clear status bits. The remaining step is to access the register corresponding to the status bit. A problem can occur when using the timer overflow function and reading the free-running counter at random times to measure an elapsed time. Without incorporating the proper precautions into software, the timer overflow flag could unintentionally be cleared if: 1. The timer status register is read or written when TOF is set. 2. The LSB of the free-running counter is read but not for the purpose of servicing the flag. The counter alternate register at addresses $1A and $1B contains the same value as the free-running counter (at address $18 and $19); therefore, this alternate register can be read at any time without affecting the timer overflow flag in the timer status register. 8.8 Timer During Wait Mode The central processor unit (CPU) clock halts during wait mode, the timer remains active. If interrupts are enabled, a timer interrupt will cause the processor to exit the wait mode. 8.9 Timer During Stop Mode In stop mode, the timer stops counting and holds the last count value if stop is exited by an interrupt. If reset is used, the counter is forced to $FFFC. During stop, if at least one valid input capture edge occurs at the TCAP pin, the input capture detect circuit is armed. This does not set any timer flags or wake up the microcontroller unit (MCU). But if the MCU exits stop due to an external interrupt, there is an active input capture flag and data from the first valid edge that occurred during the stop mode. If reset is used to exit stop mode, then no input capture flag or data remains, even if a valid input capture edge occurred. MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 MOTOROLA Timer Technical Data 67 Timer Technical Data 68 MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 Timer MOTOROLA Technical Data -- MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A Section 9. Serial Communications Interface (SCI) 9.1 Contents 9.2 9.3 9.4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 SCI Data Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 9.5 SCI Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 9.5.1 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 9.5.1.1 Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 9.5.1.2 Character Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . 72 9.5.1.3 Break Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 9.5.1.4 Idle Characters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 9.5.1.5 Transmitter Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . .74 9.5.2 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 9.5.2.1 Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 9.5.2.2 Character Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 9.5.2.3 Receiver Wakeup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 9.5.2.4 Receiver Noise Immunity . . . . . . . . . . . . . . . . . . . . . . . . . 77 9.5.2.5 Framing Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 9.5.2.6 Receiver Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 9.6 SCI Input/Output (I/O) Registers. . . . . . . . . . . . . . . . . . . . . . . . 78 9.6.1 SCI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 9.6.2 SCI Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 9.6.3 SCI Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 9.6.4 SCI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 9.6.5 Baud Rate Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 MOTOROLA Serial Communications Interface (SCI) Technical Data 69 Serial Communications Interface (SCI) 9.2 Introduction The serial communications interface (SCI) module allows high-speed asynchronous communication with peripheral devices and other microcontroller units (MCU). 9.3 Features Features of the SCI module include: * * * * * * Standard mark/space non-return-to-zero format Full duplex operation 32 programmable baud rates Programmable 8-bit or 9-bit character length Separately enabled transmitter and receiver Two receiver wakeup methods: - Idle line wakeup - Address mark wakeup * Interrupt-driven operation capability with five interrupt flags: - Transmitter data register empty - Transmission complete - Receiver data register full - Receiver overrun - Idle receiver input * * Receiver framing error detection 1/16 bit-time noise detection Technical Data 70 MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 Serial Communications Interface (SCI) MOTOROLA Serial Communications Interface (SCI) SCI Data Format 9.4 SCI Data Format The SCI uses the standard non-return-to-zero mark/space data format illustrated in Figure 9-1. 8-BIT DATA FORMAT (BIT M IN SCCR1 CLEAR) START BIT BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 STOP BIT NEXT START BIT 9-BIT DATA FORMAT (BIT M IN SCCR1 SET) START BIT BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8 STOP BIT NEXT START BIT Figure 9-1. SCI Data Format 9.5 SCI Operation The SCI allows full-duplex, asynchronous, RS232 or RS422 serial communication between the MCU and remote devices, including other MCUs. The SCI's transmitter and receiver operate independently, although they use the same baud-rate generator. This subsection describes the operation of the SCI transmitter and receiver. 9.5.1 Transmitter Figure 9-2 shows the structure of the SCI transmitter. 9.5.1.1 Character Length The transmitter can accommodate either 8-bit or 9-bit data. The state of the M bit in SCI control register 1 (SCCR1) determines character length. When transmitting 9-bit data, bit T8 in SCCR1 is the ninth bit (bit 8). MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 MOTOROLA Serial Communications Interface (SCI) Technical Data 71 Serial Communications Interface (SCI) 9.5.1.2 Character Transmission During transmission, the transmit shift register shifts a character out to the PD1/TDO pin. The SCI data register (SCDR) is the write-only buffer between the internal data bus and the transmit shift register. Writing a logic 1 to the TE bit in SCI control register 2 (SCCR2) and then writing data to the SCDR begins the transmission. At the start of a transmission, transmitter control logic automatically loads the transmit shift register with a preamble of logic 1s. After the preamble shifts out, the control logic transfers the SCDR data into the shift register. A logic 0 start bit automatically goes into the least significant bit position of the shift register, and a logic 1 stop bit goes into the most significant bit position. When the data in the SCDR transfers to the transmit shift register, the transmit data register empty (TDRE) flag in the SCI status register (SCSR) becomes set. The TDRE flag indicates that the SCDR can accept new data from the internal data bus. When the shift register is not transmitting a character, the PD1/TDO pin goes to the idle condition, logic 1. If software clears the TE bit during the idle condition, and while TDRE is set, the transmitter relinquishes control of the PD1/TDO pin. 9.5.1.3 Break Characters Writing a logic 1 to the SBK bit in SCCR2 loads the shift register with a K break character. A break character contains all logic 0s and has no start and stop bits. Break character length depends on the M bit in SCCR1. As long as SBK is at logic 1, transmitter logic continuously loads break characters into the shift register. After software clears the SBK bit, the shift register finishes transmitting the last break character and then transmits at least one logic 1. The automatic logic 1 at the end of a break character is to guarantee the recognition of the start bit of the next character. Technical Data 72 MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 Serial Communications Interface (SCI) MOTOROLA Serial Communications Interface (SCI) SCI Operation INTERNAL DATA BUS SCDR ($0011) 1X BAUD RATE CLOCK TRANSMIT SHIFT REGISTER H876543210L PIN BUFFER AND CONTROL PD1/ TDO M T8 LOAD FROM SCDR SHIFT ENABLE PREAMBLE (ALL LOGIC 1S) TRANSMITTER CONTROL LOGIC BREAK (ALL LOGIC 0S) SBK TE TDRE TIE TC TCIE SCI INTERRUPT REQUEST SCI RECEIVE REQUESTS 4 SCP0 M ILIE IDLR BIT 4 BIT 7 0 BAUD RATE REGISTER (BAUD) SCI CONTROL REGISTER 1 (SCCR1) R8 SCI CONTROL REGISTER 2 (SCCR2) TIE SCI STATUS REGISTER (SCSR) TDRE SCI DATA REGISTER (SCDR) BIT 7 6 0 T8 TCIE TC BIT 6 5 SCP1 0 RIE RDRF BIT 5 3 0 WAKE TE OR BIT 3 2 SCR2 0 RE NF BIT 2 1 SCR1 0 RWU FE BIT 1 BIT 0 SCR0 0 SBK 0 BIT 0 $000D $000E $000F $0010 $0011 Figure 9-2. SCI Transmitter MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 MOTOROLA Serial Communications Interface (SCI) Technical Data 73 Serial Communications Interface (SCI) 9.5.1.4 Idle Characters An idle character contains all logic 1s and has no start or stop bits. Idle character length depends on the M bit in SCCR1. The preamble is a synchronizing idle character that begins every transmission. Clearing the TE bit during a transmission relinquishes the PD1/TDO pin after the last character to be transmitted is shifted out. The last character may already be in the shift register, or waiting in the SCDR, or in a break character generated by writing to the SBK bit. Toggling TE from logic 0 to logic 1 while the last character is in transmission generates an idle character (a preamble) that allows the receiver to maintain control of the PD1/TDO pin. 9.5.1.5 Transmitter Interrupts Two sources can generate SCI transmitter interrupt requests: 1. Transmit data register empty (TDRE) -- The TDRE bit in the SCSR indicates that the SCDR has transferred a character to the transmit shift register. TDRE is a source of SCI interrupt requests. The transmission complete interrupt enable bit (TCIE) in SCCR2 is the local mask for TDRE interrupts. 2. Transmission complete (TC) -- The TC bit in the SCSR indicates that both the transmit shift register and the SCDR are empty and that no break or idle character has been generated. TC is a source of SCI interrupt requests. The transmission complete interrupt enable bit (TCIE) in SCCR2 is the local mask for TC interrupts. 9.5.2 Receiver Figure 9-3 shows the structure of the SCI receiver. Technical Data 74 MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 Serial Communications Interface (SCI) MOTOROLA Serial Communications Interface (SCI) SCI Operation INTERNAL DATA BUS SCDR ($0011) PD0/ RDI PIN BUFFER AND CONTROL DATA RECOVERY 8 7 6 5 4 3 2 OVERRUN 1 0 FULL IDLE BIT 0 SCR0 0 SBK 0 BIT 0 FE R8 RE M RDRF SCI INTERRUPT REQUEST RIE SCI TRANSMIT REQUESTS OR RIE IDLE ILIE WAKEUP LOGIC RWU BIT 7 0 BAUD RATE REGISTER (BAUD) SCI CONTROL REGISTER 1 (SCCR1) R8 SCI CONTROL REGISTER 2 (SCCR2) TIE SCI STATUS REGISTER (SCSR) TDRE SCI DATA REGISTER (SCDR) BIT 7 6 0 T8 TCIE TC BIT 6 5 SCP1 0 RIE RDRF BIT 5 4 SCP0 M ILIE IDLR BIT 4 3 0 WAKE TE OR BIT 3 2 SCR2 0 RE NF BIT 2 1 SCR1 0 RWU FE BIT 1 Figure 9-3. SCI Receiver MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 MOTOROLA Serial Communications Interface (SCI) MSB $000D $000E $000F $0010 $0011 NF START STOP 16X BAUD RATE CLOCK RECEIVE SHIFT REGISTER /16 Technical Data 75 Serial Communications Interface (SCI) 9.5.2.1 Character Length The receiver can accommodate either 8-bit or 9-bit data. The state of the M bit in SCI control register 1 (SCCR1) determines character length. When receiving 9-bit data, bit R8 in SCCR1 is the ninth bit (bit 8). 9.5.2.2 Character Reception During reception, the receive shift register shifts characters in from the PD0/RDI pin. The SCI data register (SCDR) is the read-only buffer between the internal data bus and the receive shift register. After a complete character shifts into the receive shift register, the data portion of the character is transferred to the SCDR, setting the receive data register full (RDRF) flag. The RDRF flag can be used to generate an interrupt. 9.5.2.3 Receiver Wakeup So that the MCU can ignore transmissions intended only for other receivers in multiple-receiver systems, the receiver can be put into a standby state. Setting the receiver wakeup enable (RWU) bit in SCI control register 2 (SCCR2) puts the receiver into a standby state during which receiver interrupts are disabled. Either of two conditions on the PD0/RDI pin can bring the receiver out of the standby state: 1. Idle input line condition -- If the PD0/RDI pin is at logic 1 long enough for 10 or 11 logic 1s to shift into the receive shift register, receiver interrupts are again enabled. 2. Address mark -- If a logic 1 occurs in the most significant bit position of a received character, receiver interrupts are again enabled. The state of the WAKE bit in SCCR1 determines which of the two conditions wakes up the MCU. Technical Data 76 MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 Serial Communications Interface (SCI) MOTOROLA Serial Communications Interface (SCI) SCI Operation 9.5.2.4 Receiver Noise Immunity The data recovery logic samples each bit 16 times to identify and verify the start bit and to detect noise. Any conflict between noise-detection samples sets the noise flag (NF) in the SCSR. The NF bit is set at the same time that the RDRF bit is set. 9.5.2.5 Framing Errors If the data recovery logic does not detect a logic 1 where the stop bit should be in an incoming character, it sets the framing error (FE) bit in the SCSR. The FE bit is set at the same time that the RDRF bit is set. 9.5.2.6 Receiver Interrupts Three sources can generate SCI receiver interrupt requests: 1. Receive data register full (RDRF) -- The RDRF bit in the SCSR indicates that the receive shift register has transferred a character to the SCDR. 2. Receiver overrun (OR) -- The OR bit in the SCSR indicates that the receive shift register shifted in a new character before the previous character was read from the SCDR. 3. Idle input (IDLE) -- The IDLE bit in the SCSR indicates that 10 or 11 consecutive logic 1s shifted in from the PD0/RDI pin. MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 MOTOROLA Serial Communications Interface (SCI) Technical Data 77 Serial Communications Interface (SCI) 9.6 SCI Input/Output (I/O) Registers These I/O registers control and monitor SCI operation: * * * * SCI data register (SCDR) SCI control register 1 (SCCR1) SCI control register 2 (SCCR2) SCI status register (SCSR) 9.6.1 SCI Data Register The SCI data register is the buffer for characters received and for characters transmitted. Address: $0011 Bit 7 Read: SCD7 Write: Reset: Unaffected by reset SDC5 SCD5 SCD4 SCD3 SCD2 SCD1 SCD0 6 5 4 3 2 1 Bit 0 Figure 9-4. SCI Data Register (SCDR) 9.6.2 SCI Control Register 1 SCI control register 1 has these functions: * * * Stores ninth SCI data bit received and ninth SCI data bit transmitted Controls SCI character length Controls SCI wakeup method Technical Data 78 MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 Serial Communications Interface (SCI) MOTOROLA Serial Communications Interface (SCI) SCI Input/Output (I/O) Registers Address: $000E Bit 7 Read: Write: Reset: = Unimplemented Unaffected by reset R8 T8 0 M WAKE 0 0 0 6 5 4 3 2 1 Bit 0 Figure 9-5. SCI Control Register 1 (SCCR1) R8 -- Bit 8 (Received) When the SCI is receiving 9-bit characters, R8 is the ninth bit of the received character. R8 receives the ninth bit from the receive shift register at the same time that the SCDR receives the other eight bits. Reset has no effect on the R8 bit. T8 -- Bit 8 (Transmitted) When the SCI is transmitting 9-bit characters, T8 is the ninth bit of the transmitted character. T8 is loaded into the transmit shift register at the same time that SCDR is loaded into the transmit shift register. Reset has no effect on the T8 bit. M -- Character Length Bit This read/write bit determines whether SCI characters are 8 bits long or 9 bits long. The ninth bit can be used as an extra stop bit, as a receiver wakeup signal, or as a mark or space parity bit. Reset has no effect on the M bit. 1 = 9-bit SCI characters 0 = 8-bit SCI characters WAKE -- Wakeup Bit This read/write bit determines which condition wakes up the SCI: a logic 1 (address mark) in the most significant bit position of a received character or an idle condition of the PD0/RDI pin. Reset has no effect on the WAKE bit. 1 = Address mark wakeup 0 = Idle line wakeup MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 MOTOROLA Serial Communications Interface (SCI) Technical Data 79 Serial Communications Interface (SCI) 9.6.3 SCI Control Register 2 SCI control register 2 has these functions: * * * * * Enables the SCI receiver and SCI receiver interrupts Enables the SCI transmitter and SCI transmitter interrupts Enables SCI receiver idle interrupts Enables SCI transmission complete interrupts Enables SCI wakeup Transmits SCI break characters Address: $000F Bit 7 Read: TIE Write: Reset: 0 0 0 0 0 0 0 0 TCIE RIE ILIE TE RE RWU SBK 6 5 4 3 2 1 Bit 0 Figure 9-6. SCI Control Register 2 (SCCR2) TIE -- Transmit Interrupt Enable Bit This read/write bit enables SCI interrupt requests when the TDRE bit becomes set. Reset clears the TIE bit. 1 = TDRE interrupt requests enabled 0 = TDRE interrupt requests disabled TCIE -- Transmission Complete Interrupt Enable Bit This read/write bit enables SCI interrupt requests when the TC bit becomes set. Reset clears the TCIE bit 1 = TC interrupt requests enabled 0 = TC interrupt requests disabled RIE -- Receive Interrupt Enable Bit This read/write bit enables SCI interrupt requests when the RDRF bit or the OR bit becomes set. Reset clears the RIE bit. 1 = RDRF interrupt requests enabled 0 = RDRF interrupt requests disabled Technical Data 80 MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 Serial Communications Interface (SCI) MOTOROLA Serial Communications Interface (SCI) SCI Input/Output (I/O) Registers ILIE -- Idle Line Interrupt Enable Bit This read/write bit enables SCI interrupt requests when the IDLE bit becomes set. Reset clears the ILIE bit. 1 = IDLE interrupt requests enabled 0 = IDLE interrupt requests disabled TE -- Transmit Enable Bit Setting this read/write bit begins the transmission by sending a preamble of 10 or 11 logic 1s from the transmit shift register to the PD1/TDO pin. Reset clears the TE bit. 1 = Transmission enabled 0 = Transmission disabled RE -- Receive Enable Bit Setting this read/write bit enables the receiver. Clearing the RE bit disables the receiver and receiver interrupts but does not affect the receiver interrupt flags. Reset clears the RE bit. 1 = Receiver enabled 0 = Receiver disabled RWU -- Receiver Wakeup Enable Bit This read/write bit puts the receiver in a standby state. Typically, data transmitted to the receiver clears the RWU bit and returns the receiver to normal operation. The WAKE bit in SCCR1 determines whether an idle input or an address mark brings the receiver out of the standby state. Reset clears the RWU bit. 1 = Standby state 0 = Normal operation SBK -- Send Break Bit Setting this read/write bit continuously transmits break codes in the form of 10-bit or 11-bit groups of logic 0s. Clearing the SBK bit stops the break codes and transmits a logic 1 as a start bit. Reset clears the SBK bit. 1 = Break codes being transmitted 0 = No break codes being transmitted MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 MOTOROLA Serial Communications Interface (SCI) Technical Data 81 Serial Communications Interface (SCI) 9.6.4 SCI Status Register The SCI status register contains flags to signal these conditions: * * * * * * * Address: Transfer of SCDR data to transmit shift register complete Transmission complete Transfer of receive shift register data to SCDR complete Receiver input idle Receiver overrun Noisy data Framing error $0010 Bit 7 6 TC 5 RDRF 4 IDLE 3 OR 2 NF 1 FE 0 Bit 0 Read: Write: Reset: TDRE 0 0 0 0 0 0 0 0 = Unimplemented Figure 9-7. SCI Status Register (SCSR) TDRE -- Transmit Data Register Empty Bit This clearable, read-only bit is set when the data in the SCDR transfers to the transmit shift register. TDRE generates an interrupt request if the TIE bit in SCCR2 is also set. Clear the TDRE bit by reading the SCSR with TDRE set, and then writing to the SCDR. Reset sets the TDRE bit. Software must initialize the TDRE bit to logic 0 to avoid an instant interrupt request when turning on the transmitter. 1 = SCDR data transferred to transmit shift register 0 = SCDR data not transferred to transmit shift register TC -- Transmission Complete Bit This clearable, read-only bit is set when the TDRE bit is set, and no data, preamble, or break character is being transmitted. TC generates an interrupt request if the TCIE bit in SCCR2 is also set. Clear the TC bit by reading the SCSR with TC set, and then writing to the SCDR. Technical Data 82 MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 Serial Communications Interface (SCI) MOTOROLA Serial Communications Interface (SCI) SCI Input/Output (I/O) Registers Reset sets the TC bit. Software must initialize the TC bit to logic 0 to avoid an instant interrupt request when turning on the transmitter. 1 = No transmission in progress 0 = Transmission in progress RDRF -- Receive Data Register Full Bit This clearable, read-only bit is set when the data in the receive shift register transfers to the SCI data register. RDRF generates an interrupt request if the RIE bit in SCCR2 is also set. Clear the RDRF bit by reading the SCSR with RDRF set, and then reading the SCDR. Reset clears the RDRF bit. 1 = Received data available in SCDR 0 = Received data not available in SCDR IDLE -- Receiver Idle Bit This clearable, read-only bit is set when 10 or 11 consecutive logic 1s appear on the receiver input. IDLE generates an interrupt request if the ILIE bit in SCCR2 is also set. Clear the IDLE bit by reading the SCSR with IDLE set, and then reading the SCDR. Reset clears the IDLE bit. 1 = Receiver input idle 0 = Receiver input not idle OR -- Receiver Overrun Bit This clearable, read-only bit is set if the SCDR is not read before the receive shift register receives the next word. OR generates an interrupt request if the RIE bit in SCCR2 is also set. The data in the shift register is lost, but the data already in the SCDR is not affected. Clear the OR bit by reading the SCSR with OR set and then reading the SCDR. Reset clears the OR bit. 1 = Receiver shift register full and RDRF = 1 0 = No receiver overrun NF -- Receiver Noise Flag This clearable, read-only bit is set when noise is detected in data received in the SCI data register. Clear the NF bit by reading the SCSR and then reading the SCDR. Reset clears the NF bit. 1 = Noise detected in SCDR 0 = No noise detected in SCDR MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 MOTOROLA Serial Communications Interface (SCI) Technical Data 83 Serial Communications Interface (SCI) FE -- Receiver Framing Error Flag This clearable, read-only flag is set when there is a logic 0 where a stop bit should be in the character shifted into the receive shift register. If the received word causes both a framing error and an overrun error, the OR bit is set and the FE bit is not set. Clear the FE bit by reading the SCSR, and then reading the SCDR. Reset clears the FE bit. 1 = Framing error 0 = No framing error 9.6.5 Baud Rate Register The baud rate register (BAUD) selects the baud rate for both the receiver and the transmitter. Address: $000D Bit 7 Read: 0 Write: Reset: 0 U = Unaffected 0 0 0 0 U U U 0 SCP1 SCP0 0 SCR2 SCR2 SCR0 6 5 4 3 2 1 Bit 0 Figure 9-8. Baud Rate Register (BAUD) SCP1 and SCP0 -- SCI Prescaler Select Bits These read/write bits control prescaling of the baud rate generator clock, as shown in Table 9-1. Resets clear both SCP1 and SCP0. Table 9-1. Baud Rate Generator Clock Prescaling SCP0-SCP1 00 01 10 11 Baud Rate Generator Clock Internal clock divided by 1 Internal clock divided by 3 Internal clock divided by 4 Internal clock divided by 13 Technical Data 84 MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 Serial Communications Interface (SCI) MOTOROLA Serial Communications Interface (SCI) SCI Input/Output (I/O) Registers SCR2-SCR0 -- SCI Baud Rate Select Bits These read/write bits select the SCI baud rate, as shown in Table 9-2. Reset has no effect on the SCR2-SCR0 bits. Table 9-2. Baud Rate Selection SCR2-SCR0 000 001 010 011 100 101 110 111 SCI Baud Rate (Baud) Prescaled clock divided by 1 Prescaled clock divided by 2 Prescaled clock divided by 4 Prescaled clock divided by 8 Prescaled clock divided by 16 Prescaled clock divided by 32 Prescaled clock divided by 64 Prescaled clock divided by 128 Table 9-3 shows all possible SCI baud rates derived from crystal frequencies of 2 MHz, 4 MHz, and 4.194304 MHz. MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 MOTOROLA Serial Communications Interface (SCI) Technical Data 85 Serial Communications Interface (SCI) Table 9-3. Baud Rate Selection Examples SCP[1:0] 00 00 00 00 00 00 00 00 01 01 01 01 01 01 01 01 10 10 10 10 10 10 10 10 11 11 11 11 11 11 11 11 SCR [2:1:0] 000 001 010 011 100 101 110 111 000 001 010 011 100 101 110 111 000 001 010 011 100 101 110 111 000 001 010 011 100 101 110 111 SCI Baud Rate fOSC = 2 MHz 62.50 kBaud 31.25 kBaud 15.63 kBaud 7813 Baud 3906 Baud 1953 Baud 976.6 Baud 488.3 Baud 20.83 kBaud 10.42 kBaud 5208 Baud 2604 Baud 1302 Baud 651.0 Baud 325.5 Baud 162.8 Baud 15.63 kBaud 7813 Baud 3906 Baud 1953 Baud 976.6 Baud 488.3 Baud 244.1 Baud 122.1 Baud 4808 Baud 2404 Baud 1202 Baud 601.0 Baud 300.5 Baud 150.2 Baud 75.12 Baud 37.56 Baud fOSC = 4 MHz 125 kBaud 62.50 kBaud 31.25 kBaud 15.63 kBaud 7813 Baud 3906 Baud 1953 Baud 976.6 Baud 41.67 kBaud 20.83 kBaud 10.42 kBaud 5208 Baud 2604 Baud 1302 Baud 651.0 Baud 325.5 Baud 31.25 kBaud 15.63 kBaud 7813 Baud 3906 Baud 1953 Baud 976.6 Baud 488.3 Baud 244.1 Baud 9615 Baud 4808 Baud 2404 Baud 1202 Baud 601.0 Baud 300.5 Baud 150.2 Baud 75.12 Baud fOSC = 4.194304 MHz 131.1 kBaud 65.54 kBaud 32.77 kBaud 16.38 kBaud 8192 Baud 4096 Baud 2048 Baud 1024 Baud 43.69 kBaud 21.85 kBaud 10.92 kBaud 5461 Baud 2731 Baud 1365 Baud 682.7 Baud 341.3 Baud 32.77 kBaud 16.38 kBaud 8192 Baud 4906 Baud 2048 Baud 1024 Baud 512.0 Baud 256.0 Baud 10.08 kBaud 5041 Baud 2521 Baud 1260 Baud 630.2 Baud 315.1 Baud 157.5 Baud 78.77 Baud Technical Data 86 MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 Serial Communications Interface (SCI) MOTOROLA Technical Data -- MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A A Section 10. Serial Peripheral Interface (SPI) 10.1 Contents 10.2 10.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 10.4 SPI Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 10.4.1 Master In Slave Out (MISO) . . . . . . . . . . . . . . . . . . . . . . . . . 88 10.4.2 Master Out Slave In (MOSI) . . . . . . . . . . . . . . . . . . . . . . . . . 88 10.4.3 Serial Clock (SCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 10.4.4 Slave Select (SS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 10.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 10.6 SPI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 10.6.1 Serial Peripheral Control Register . . . . . . . . . . . . . . . . . . . . 93 10.6.2 Serial Peripheral Status Register . . . . . . . . . . . . . . . . . . . . .94 10.6.3 Serial Peripheral Data I/O Register . . . . . . . . . . . . . . . . . . . 96 10.2 Introduction The serial peripheral interface (SPI) is an interface built into the MC68HC05 microcontroller unit (MCU) which allows several MC68HC05 MCUs or MC68HC05 MCU plus peripheral devices to be interconnected within a single printed circuit board. In an SPI, separate wires are required for data and clock. In the SPI format, the clock is not included in the data stream and must be furnished as a separate signal. An SPI system may be configured in a system containing one master MCU and several slave MCUs or in a system in which an MCU is capable of being a master or a slave. MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 MOTOROLA Serial Peripheral Interface (SPI) Technical Data 87 Serial Peripheral Interface (SPI) 10.3 Features * * * * * * * * * Full duplex, 4-wire synchronous transfers Master or slave operation Bus frequency divided by 2 (maximum) master bit frequency Bus frequency (maximum) slave bit frequency Four programmable master bit rates Programmable clock polarity and phase End-of-transmission interrupt flag Write collision flag protection Master-master mode fault protection capability 10.4 SPI Signal Description gnal The four basic signals (MOSI, MISO, SCK, and SS) are described in this subsection. Each signal function is described for both the master and slave mode. 10.4.1 Master In Slave Out (MISO) The MISO line is configured as an input in a master device and as an output in a slave device. It is one of the two lines that transfer serial data in one direction, with the most significant bit sent first. The MISO line of a slave device is placed in the high-impedance state if the slave is not selected. 10.4.2 Master Out Slave In (MOSI) The MOSI line is configured as an output in a master device and as an input in a slave device. It is one of the two lines that transfer serial data in one direction with the most significant bit sent first. Technical Data 88 MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 Serial Peripheral Interface (SPI) MOTOROLA Serial Peripheral Interface (SPI) SPI Signal Description 10.4.3 Serial Clock (SCK) The master clock is used to synchronize data movement both in and out of the device through its MOSI and MISO lines. The master and slave devices are capable of exchanging a byte of information during a sequence of eight clock cycles. Since SCK is generated by the master device, this line becomes an input on a slave device. As shown in Figure 10-1, four possible timing relationships may be chosen by using control bits CPOL and CPHA in the serial peripheral control register (SPCR). Both master and slave devices must operate with the same timing. The master device always places data on the MOSI line one-half cycle before the clock edge (SCK), so the slave device can latch the data. Two bits (SPR0 and SPR1) in the SPCR of the master device select the clock rate. In a slave device, SPR0 and SPR1 have no effect on the SPI operation. SS SCK SCK SCK SCK MISO/MOSI MSB 6 5 4 3 2 1 0 INTERNAL STROBE FOR DATA CAPTURE (ALL MODES) Figure 10-1. Data Clock Timing Diagram MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 MOTOROLA Serial Peripheral Interface (SPI) Technical Data 89 Serial Peripheral Interface (SPI) 10.4.4 Slave Select (SS) The slave select (SS) input line is used to select a slave device. It has to be low prior to data transactions and must stay low for the duration of the transaction. The SS line on the master must be tied high. If it goes low, a mode fault error flag (MODF) is set in the SPSR. When CPHA = 0, the shift clock is the OR of SS with SCK. In this clock phase mode, SS must go high between successive characters in an SPI message. When CPHA = 1, SS may be left low for several SPI characters. In cases where there is only one SPI slave MCU, its SS line could be tied to VSS as long as CPHA = 1 clock modes are used. 10.5 Functional Description Figure 10-2 shows a block diagram of the SPI circuitry. When a master device transmits data to a slave via the MOSI line, the slave device responds by sending data to the master device via the master's MISO line. This implies full duplex transmission with both data out and data in synchronized with the same clock signal. Thus, the byte transmitted is replaced by the byte received and eliminates the need for separate transmit-empty and receive-full status bits. A single status bit (SPIF) is used to signify that the input/output (I/O) operation has been completed. The SPI data register (SPDR) is double buffered on read, but not on write. If a write is performed during data transfer, the transfer occurs uninterrupted, and the write will be unsuccessful. This condition will cause the write collision (WCOL) status bit in the SPSR to be set. After a data byte is shifted, the SPIF flag of the SPSR is set. In the master mode, the SCK pin is an output. It idles high or low, depending on the CPOL bit in the SPCR, until data is written to the shift register, at which point eight clocks are generated to shift the eight bits of data and then SCK goes idle again. Technical Data 90 MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 Serial Peripheral Interface (SPI) MOTOROLA Serial Peripheral Interface (SPI) Functional Description S M INTERNAL MCU CLOCK MSB 8-BIT SHIFT REG DIVIDER READ DATA BUFF /2 /4 / 16 / 32 PIN CONTROL LOGIC LSB MISO PD2 M S MOSI PD3 SELECT SPI CLOCK (MASTER) CLOCK CLOCK LOGIC S M SCK PD4 SPR1 SPR0 SS PD5 MSTR SPI CONTROL SPE MSTR CPHA CPOL SPR1 WCOL MODF SPIF SPI STATUS REGISTER SPI CONTROL REGISTER INTERNAL DATA BUS SPI INTERRUPT REQUEST Figure 10-2. Serial Peripheral Interface Block Diagram MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 MOTOROLA Serial Peripheral Interface (SPI) SPR0 SPIE SPE Technical Data 91 Serial Peripheral Interface (SPI) In a slave mode, the slave select start logic receives a logic low at the SS pin and a clock at the SCK pin. Thus, the slave is synchronized with the master. Data from the master is received serially at the MOSI line and loads the 8-bit shift register. After the 8-bit shift register is loaded, its data is parallel transferred to the read buffer. During a write cycle, data is written into the shift register, then the slave waits for a clock train from the master to shift the data out on the slave's MISO line. Figure 10-3 illustrates the MOSI, MISO, SCK, and SS master-slave interconnections. PD3/MOSI SPI SHIFT REGISTER PD2/MISO SPI SHIFT REGISTER I/O PORT PD5 SS SPDR ($000C) PD4/SCK SPDR ($000C) MASTER MCU SLAVE MCU Figure 10-3. Serial Peripheral Interface Master-Slave Interconnection 10.6 SPI Registers This subsection describes the three registers in the SPI which provide control, status, and data storage functions. These registers are: * * * Serial peripheral control register (SPCR) Serial peripheral status register (SPSR) Serial peripheral data I/O register (SPDR) Technical Data 92 MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 Serial Peripheral Interface (SPI) MOTOROLA Serial Peripheral Interface (SPI) SPI Registers 10.6.1 Serial Peripheral Control Register Address: $000A Bit 7 Read: SPIE Write: Reset 0 0 0 0 0 U = Unaffected 0 U U SPE MSTR CPOL CPHA SPR1 SPR0 6 5 4 3 2 1 Bit 0 = Unimplemented Figure 10-4. SPI Control Register (SPCR) SPIE -- Serial Peripheral Interrupt Enable Bit 0 = SPIF interrupts disabled 1 = SPI interrupt is enabled SPE -- Serial Peripheral System Enable Bit 0 = SPI system off 1 = SPI system on MSTR -- Master Mode Select Bit 0 = Slave mode 1 = Master mode CPOL -- Clock Polarity Bit When the clock polarity bit is cleared and data is not being transferred, a steady state low value is produced at the SCK pin of the master device. Conversely, if this bit is set, the SCK pin will idle high. This bit also is used in conjunction with the clock phase control bit to produce the desired clock-data relationship between master and slave. See Figure 10-1. CPHA -- Clock Phase Bit The clock phase bit, in conjunction with the CPOL bit, controls the clock-data relationship between master and slave. The CPOL bit can be thought of as simply inserting an inverter in series with the SCK line. The CPHA bit selects one of two fundamentally different clocking protocols. When CPHA = 0, the shift clock is the OR of SCK with SS. MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 MOTOROLA Serial Peripheral Interface (SPI) Technical Data 93 Serial Peripheral Interface (SPI) As soon as SS goes low, the transaction begins and the first edge on SCK invokes the first data sample. When CPHA = 1, the SS pin may be thought of as a simple output enable control. See Figure 10-1. SPR1 and SPR0 -- SPI Clock Rate Select Bits These two bits select one of four baud rates to be used as SCK if the device is a master; however, they have no effect in the slave mode. See Table 10-1. Table 10-1. Serial Peripheral Rate Selection SPR1 0 0 1 1 SPR0 0 1 0 1 Bus Clock Divided By 2 4 16 32 10.6.2 Serial Peripheral Status Register Address: $000B Bit 7 Read: SPIF Write: Reset 0 0 0 0 0 U = Unaffected 0 U U WCOL 6 5 0 MODF 4 3 0 2 0 1 0 Bit 0 0 = Unimplemented Figure 10-5. SPI Status Register (SPSR) SPIF -- SPI Transfer Complete Flag The serial peripheral data transfer flag bit is set upon completion of data transfer between the processor and external device. If SPIF goes high and if SPIE is set, a serial peripheral interrupt is generated. Clearing the SPIF bit is accomplished by reading the SPSR (with SPIF set) followed by an access of the SPDR. Unless SPSR is read (with SPIF set) first, attempts to write to SPDR are inhibited. Technical Data 94 MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 Serial Peripheral Interface (SPI) MOTOROLA Serial Peripheral Interface (SPI) SPI Registers WCOL -- Write Collision Bit The write collision bit is set when an attempt is made to write to the serial peripheral data register while data transfer is taking place. If CPHA is 0, a transfer is said to begin when SS goes low and the transfer ends when SS goes high after eight clock cycles on SCK. When CPHA is 1, a transfer is said to begin the first time SCK becomes active while SS is low. The transfer ends when the SPIF flag gets set. Clearing the WCOL bit is accomplished by reading the SPSR (with WCOL set) followed by an access to SPDR. Bit 5 -- Not implemented This bit always reads as 0. MODF -- Mode Fault Flag The mode fault flag indicates that there may have been a multi-master conflict for system control and allows a proper exit from system operation to a reset or default system state. The MODF bit is normally clear and is set only when the master device has its SS pin pulled low. Setting the MODF bit affects the internal serial peripheral interface system in these ways: *An SPI interrupt is generated if SPIE = 1. *The SPE bit is cleared. This disables the SPI. *The MSTR bit is cleared, thus forcing the device into the slave mode. Clearing the MODF bit is accomplished by reading the SPSR (with MODF set), followed by a write to the SPCR. Control bits SPE and MSTR may be restored by user software to their original state after the MODF bit has been cleared. Bits 3-0 -- Not Implemented These bits always reads as 0. MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 MOTOROLA Serial Peripheral Interface (SPI) Technical Data 95 Serial Peripheral Interface (SPI) 10.6.3 Serial Peripheral Data I/O Register Address: $000C Bit 7 Read: SPD7 Write: Reset Unaffected by reset SPD6 SPD5 SPD4 SPD3 SPD2 SPD1 SPD0 6 5 4 3 2 1 Bit 0 Figure 10-6. SPI Data Register (SPSR) The serial peripheral data I/O register is used to transmit and receive data on the serial bus. Only a write to this register will initiate transmission/reception of another byte, and this will occur only in the master device. At the completion of transmitting a byte of data, the SPIF status bit is set in both the master and slave devices. When the user reads the serial peripheral data I/O register, a buffer is actually being read. The first SPIF must be cleared by the time a second transfer of the data from the shift register to the read buffer is initiated or an overrun condition will exist. In cases of overrun, the byte which causes the overrun is lost. A write to the serial peripheral data I/O register is not buffered and places data directly into the shift register for transmission. Technical Data 96 MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 Serial Peripheral Interface (SPI) MOTOROLA Technical Data -- MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A L05C8A Section 11. Operating Modes 11.1 Contents 11.2 11.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 User Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 11.4 Self-Check Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 11.4.1 Self-Check Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 11.4.2 Self-Check Results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 11.2 Introduction The microcontroller unit (MCU) has two modes of operation: user mode and self-check mode. Table 11-1 shows the conditions required to enter into each mode, where VTST = 2 x VDD. Table 11-1. Operating Mode Conditions RESET IRQ VSS to VDD VTST TCAP VSS to VDD VDD Mode User Self-Check MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 MOTOROLA Operating Modes Technical Data 97 Operating Modes 11.3 User Mode In user mode, the address and data buses are not available externally, but there are three 8-bit input/output (I/O) ports and one 7-bit input-only port. This mode allows the MCU to function as a self-contained microcontroller, with maximum use of the pins for on-chip peripheral functions. All address and data activity occurs within the MCU. User mode is entered on the rising edge of RESET if the IRQ pin is within normal operating range. RESET IRQ NC PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VDD OSC1 OSC2 TCAP PD7 PD6/TCMP PD5/SS PD4/SCK PD3/MOSI PD2/MISO PD1/TDO PD0/RDI PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 Figure 11-1. User Mode Pinout Technical Data 98 MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 Operating Modes MOTOROLA Operating Modes Self-Check Mode 11.4 Self-Check Mode k Self-check mode is entered upon the rising edge of RESET if the IRQ pin is at VTST and the TCAP pin is at logic 1. 11.4.1 Self-Check Tests The self-check read-only memory (ROM) at mask ROM location $1F00-$1FEF determines if the MCU is functioning properly.These tests are performed: 1. I/O -- Functional test of ports A, B, and C 2. Random-access memory (RAM) -- Counter test for each RAM byte 3. Timer -- Test of counter register and OCF bit 4. Serial communications interface (SCI) -- Transmission test checks for RDRF, TDRE, TC, and FE flags 5. Read-only memory (ROM) -- Exclusive OR with odd ones parity result 6. Serial peripheral interface (SPI) -- Transmission test checks for SPIF and WCOL flags The self-check circuit is shown in Figure 11-2. MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 MOTOROLA Operating Modes Technical Data 99 Operating Modes 11.4.2 Self-Check Results Table 11-2 shows the light-emitting diode (LED) codes that indicate selfcheck test results. Table 11-2. Self-Check Circuit LED Codes PC3 Off Off Off Off Off Off PC2 On On On Off Off Off Flashing All others PC1 On Off Off On On Off PC0 Off On Off On Off On Remarks I/O failure RAM failure Timer failure SCI failure ROM failure SPI failure No failure Device failure Perform these steps to activate the self-check tests: 1. Apply 10 V (2 x VDD) to the IRQ pin. 2. Apply a logic 1 to the TCAP pin. 3. Apply a logic 0 to the RESET pin. The self-check tests begin on the rising edge of the RESET pin. RESET must be held low for 4064 cycles after power-on reset (POR) or for a time, tRL, for any other reset. For the tRL value, see 13.9 5.0-V Control Timing. Technical Data 100 MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 Operating Modes MOTOROLA Operating Modes Self-Check Mode V DD V DD 10 V MC34064 4.7 k RESET IRQ NC PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 V SS V MC68H05C8A V DD DD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 OSC1 OSC2 TCAP PD7 TCMP PD5/SS PD4/SCK PD3/MOSI PD2/MISO PD1/TDO PD0/RDI PC0 PC1 PC2 PC3 PC4 PC5 PC6 330 330 330 PC7 330 VDD CMOS BUFFER (MC74HC125) 1 M VDD 10 M 10 k 20 pF 20 pF 4 MHZ Notes: 1. VDD = 5.0 V 2. TCMP = NC Figure 11-2. Self-Check Circuit Schematic MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 MOTOROLA Operating Modes Technical Data 101 Operating Modes Technical Data 102 MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 Operating Modes MOTOROLA Technical Data -- MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A Section 12. Instruction Set 12.1 Contents 12.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 12.3 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 12.3.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 12.3.2 Immediate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 12.3.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 12.3.4 Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 12.3.5 Indexed, No Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 12.3.6 Indexed, 8-Bit Offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 12.3.7 Indexed, 16-Bit Offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 12.3.8 Relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 12.4 Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 12.4.1 Register/Memory Instructions. . . . . . . . . . . . . . . . . . . . . . . 108 12.4.2 Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . . 109 12.4.3 Jump/Branch Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . 110 12.4.4 Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . .112 12.4.5 Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 12.5 12.6 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 MOTOROLA Instruction Set Technical Data 103 Instruction Set 12.2 Introduction The microcontroller unit (MCU) instruction set has 62 instructions and uses eight addressing modes. The instructions include all those of the M146805 CMOS (complementary metal oxide silicon) Family plus one more: the unsigned multiply (MUL) instruction. The MUL instruction allows unsigned multiplication of the contents of the accumulator (A) and the index register (X). The high-order product is stored in the index register, and the low-order product is stored in the accumulator. 12.3 Addressing Modes The central processor unit (CPU) uses eight addressing modes for flexibility in accessing data. The addressing modes provide eight different ways for the CPU to find the data required to execute an instruction. The eight addressing modes are: * * * * * * * * Inherent Immediate Direct Extended Indexed, no offset Indexed, 8-bit offset Indexed, 16-bit offset Relative Technical Data 104 MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 Instruction Set MOTOROLA Instruction Set Addressing Modes 12.3.1 Inherent Inherent instructions are those that have no operand, such as return from interrupt (RTI) and stop (STOP). Some of the inherent instructions act on data in the CPU registers, such as set carry flag (SEC) and increment accumulator (INCA). Inherent instructions require no operand address and are one byte long. 12.3.2 Immediate Immediate instructions are those that contain a value to be used in an operation with the value in the accumulator or index register. Immediate instructions require no operand address and are two bytes long. The opcode is the first byte, and the immediate data value is the second byte. 12.3.3 Direct Direct instructions can access any of the first 256 memory locations with two bytes. The first byte is the opcode, and the second is the low byte of the operand address. In direct addressing, the CPU automatically uses $00 as the high byte of the operand address. 12.3.4 Extended Extended instructions use three bytes and can access any address in memory. The first byte is the opcode; the second and third bytes are the high and low bytes of the operand address. When using the Motorola assembler, the programmer does not need to specify whether an instruction is direct or extended. The assembler automatically selects the shortest form of the instruction. MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 MOTOROLA Instruction Set Technical Data 105 Instruction Set 12.3.5 Indexed, No Offset Indexed instructions with no offset are 1-byte instructions that can access data with variable addresses within the first 256 memory locations. The index register contains the low byte of the effective address of the operand. The CPU automatically uses $00 as the high byte, so these instructions can address locations $0000-$00FF. Indexed, no offset instructions are often used to move a pointer through a table or to hold the address of a frequently used random-access memory (RAM) or input/output (I/O) location. 12.3.6 Indexed, 8-Bit Offset Indexed, 8-bit offset instructions are 2-byte instructions that can access data with variable addresses within the first 511 memory locations. The CPU adds the unsigned byte in the index register to the unsigned byte following the opcode. The sum is the effective address of the operand. These instructions can access locations $0000-$01FE. Indexed 8-bit offset instructions are useful for selecting the kth element in an n-element table. The table can begin anywhere within the first 256 memory locations and could extend as far as location 510 ($01FE). The k value is typically in the index register, and the address of the beginning of the table is in the byte following the opcode. 12.3.7 Indexed, 16-Bit Offset Indexed, 16-bit offset instructions are 3-byte instructions that can access data with variable addresses at any location in memory. The CPU adds the unsigned byte in the index register to the two unsigned bytes following the opcode. The sum is the effective address of the operand. The first byte after the opcode is the high byte of the 16-bit offset; the second byte is the low byte of the offset. Indexed, 16-bit offset instructions are useful for selecting the kth element in an n-element table anywhere in memory. Technical Data 106 MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 Instruction Set MOTOROLA Instruction Set Instruction Types As with direct and extended addressing, the Motorola assembler determines the shortest form of indexed addressing. 12.3.8 Relative Relative addressing is only for branch instructions. If the branch condition is true, the CPU finds the effective branch destination by adding the signed byte following the opcode to the contents of the program counter. If the branch condition is not true, the CPU goes to the next instruction. The offset is a signed, two's complement byte that gives a branching range of -128 to +127 bytes from the address of the next location after the branch instruction. When using the Motorola assembler, the programmer does not need to calculate the offset, because the assembler determines the proper offset and verifies that it is within the span of the branch. 12.4 Instruction Types 4 The MCU instructions fall into the following five categories: * * * * * Register/Memory instructions Read-Modify-Write instructions Jump/Branch instructions Bit Manipulation instructions Control instructions MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 MOTOROLA Instruction Set Technical Data 107 Instruction Set 12.4.1 Register/Memory Instructions These instructions operate on CPU registers and memory locations. Most of them use two operands. One operand is in either the accumulator or the index register. The CPU finds the other operand in memory. Table 12-1. Register/Memory Instructions Instruction Add Memory Byte and Carry Bit to Accumulator Add Memory Byte to Accumulator AND Memory Byte with Accumulator Bit Test Accumulator Compare Accumulator Compare Index Register with Memory Byte EXCLUSIVE OR Accumulator with Memory Byte Load Accumulator with Memory Byte Load Index Register with Memory Byte Multiply OR Accumulator with Memory Byte Subtract Memory Byte and Carry Bit from Accumulator Store Accumulator in Memory Store Index Register in Memory Subtract Memory Byte from Accumulator Mnemonic ADC ADD AND BIT CMP CPX EOR LDA LDX MUL ORA SBC STA STX SUB Technical Data 108 MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 Instruction Set MOTOROLA Instruction Set Instruction Types 12.4.2 Read-Modify-Write Instructions These instructions read a memory location or a register, modify its contents, and write the modified value back to the memory location or to the register. NOTE: Do not use read-modify-write operations on write-only registers. Table 12-2. Read-Modify-Write Instructions Instruction Arithmetic Shift Left (Same as LSL) Arithmetic Shift Right Bit Clear Bit Set Clear Register Complement (One's Complement) Decrement Increment Logical Shift Left (Same as ASL) Logical Shift Right Negate (Two's Complement) Rotate Left through Carry Bit Rotate Right through Carry Bit Test for Negative or Zero Mnemonic ASL ASR BCLR(1) BSET(1) CLR COM DEC INC LSL LSR NEG ROL ROR TST(2) 1. Unlike other read-modify-write instructions, BCLR and BSET use only direct addressing. 2. TST is an exception to the read-modify-write sequence because it does not write a replacement value. MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 MOTOROLA Instruction Set Technical Data 109 Instruction Set 12.4.3 Jump/Branch Instructions Jump instructions allow the CPU to interrupt the normal sequence of the program counter. The unconditional jump instruction (JMP) and the jump-to-subroutine instruction (JSR) have no register operand. Branch instructions allow the CPU to interrupt the normal sequence of the program counter when a test condition is met. If the test condition is not met, the branch is not performed. The BRCLR and BRSET instructions cause a branch based on the state of any readable bit in the first 256 memory locations. These 3-byte instructions use a combination of direct addressing and relative addressing. The direct address of the byte to be tested is in the byte following the opcode. The third byte is the signed offset byte. The CPU finds the effective branch destination by adding the third byte to the program counter if the specified bit tests true. The bit to be tested and its condition (set or clear) is part of the opcode. The span of branching is from -128 to +127 from the address of the next location after the branch instruction. The CPU also transfers the tested bit to the carry/borrow bit of the condition code register. Technical Data 110 MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 Instruction Set MOTOROLA Instruction Set Instruction Types Table 12-3. Jump and Branch Instructions Instruction Branch if Carry Bit Clear Branch if Carry Bit Set Branch if Equal Branch if Half-Carry Bit Clear Branch if Half-Carry Bit Set Branch if Higher Branch if Higher or Same Branch if IRQ Pin High Branch if IRQ Pin Low Branch if Lower Branch if Lower or Same Branch if Interrupt Mask Clear Branch if Minus Branch if Interrupt Mask Set Branch if Not Equal Branch if Plus Branch Always Branch if Bit Clear Branch Never Branch if Bit Set Branch to Subroutine Unconditional Jump Jump to Subroutine Mnemonic BCC BCS BEQ BHCC BHCS BHI BHS BIH BIL BLO BLS BMC BMI BMS BNE BPL BRA BRCLR BRN BRSET BSR JMP JSR MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 MOTOROLA Instruction Set Technical Data 111 Instruction Set 12.4.4 Bit Manipulation Instructions The CPU can set or clear any writable bit in the first 256 bytes of memory, which includes I/O registers and on-chip RAM locations. The CPU can also test and branch based on the state of any bit in any of the first 256 memory locations. Table 12-4. Bit Manipulation Instructions Instruction Bit Clear Branch if Bit Clear Branch if Bit Set Bit Set Mnemonic BCLR BRCLR BRSET BSET 12.4.5 Control Instructions These instructions act on CPU registers and control CPU operation during program execution. Table 12-5. Control Instructions Instruction Clear Carry Bit Clear Interrupt Mask No Operation Reset Stack Pointer Return from Interrupt Return from Subroutine Set Carry Bit Set Interrupt Mask Stop Oscillator and Enable IRQ Pin Software Interrupt Transfer Accumulator to Index Register Transfer Index Register to Accumulator Stop CPU Clock and Enable Interrupts Mnemonic CLC CLI NOP RSP RTI RTS SEC SEI STOP SWI TAX TXA WAIT Technical Data 112 MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 Instruction Set MOTOROLA Instruction Set Instruction Set Summary 12.5 Instruction Set Summary Table 12-6. Instruction Set Summary (Sheet 1 of 6) Opcode Source Form ADC #opr ADC opr ADC opr ADC opr,X ADC opr,X ADC ,X ADD #opr ADD opr ADD opr ADD opr,X ADD opr,X ADD ,X AND #opr AND opr AND opr AND opr,X AND opr,X AND ,X ASL opr ASLA ASLX ASL opr,X ASL ,X ASR opr ASRA ASRX ASR opr,X ASR ,X BCC rel Operation Description H I NZC Add with Carry A (A) + (M) + (C) -- IMM DIR EXT IX2 IX1 IX IMM DIR EXT IX2 IX1 IX IMM DIR EXT IX2 IX1 IX DIR INH INH IX1 IX DIR INH INH IX1 IX REL 2 A9 ii B9 dd 3 C9 hh ll 4 D9 ee ff 5 4 E9 ff 3 F9 2 AB ii BB dd 3 CB hh ll 4 DB ee ff 5 4 EB ff 3 FB 2 A4 ii B4 dd 3 C4 hh ll 4 D4 ee ff 5 4 E4 ff 3 F4 38 48 58 68 78 37 47 57 67 77 24 11 13 15 17 19 1B 1D 1F 25 27 28 29 22 dd 5 3 3 6 5 5 3 3 6 5 3 5 5 5 5 5 5 5 5 3 3 3 3 3 Add without Carry A (A) + (M) -- Logical AND A (A) (M) ---- -- Arithmetic Shift Left (Same as LSL) C b7 b0 0 ---- ff dd Arithmetic Shift Right b7 b0 C ---- ff rr dd dd dd dd dd dd dd dd rr rr rr rr rr Branch if Carry Bit Clear PC (PC) + 2 + rel ? C = 0 ---------- BCLR n opr Clear Bit n Mn 0 DIR (b0) DIR (b1) DIR (b2) DIR (b3) ---------- DIR (b4) DIR (b5) DIR (b6) DIR (b7) ---------- ---------- ---------- ---------- REL REL REL REL REL BCS rel BEQ rel BHCC rel BHCS rel BHI rel Branch if Carry Bit Set (Same as BLO) Branch if Equal Branch if Half-Carry Bit Clear Branch if Half-Carry Bit Set Branch if Higher PC (PC) + 2 + rel ? C = 1 PC (PC) + 2 + rel ? Z = 1 PC (PC) + 2 + rel ? H = 0 PC (PC) + 2 + rel ? H = 1 PC (PC) + 2 + rel ? C Z = 0 -- -- -- -- -- MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 MOTOROLA Instruction Set Technical Data 113 Cycles Effect on CCR Operand Address Mode Instruction Set Table 12-6. Instruction Set Summary (Sheet 2 of 6) Opcode Source Form BHS rel BIH rel BIL rel BIT #opr BIT opr BIT opr BIT opr,X BIT opr,X BIT ,X BLO rel BLS rel BMC rel BMI rel BMS rel BNE rel BPL rel BRA rel Operation Branch if Higher or Same Branch if IRQ Pin High Branch if IRQ Pin Low Description PC (PC) + 2 + rel ? C = 0 PC (PC) + 2 + rel ? IRQ = 1 PC (PC) + 2 + rel ? IRQ = 0 H I NZC ---------- ---------- ---------- REL REL REL IMM DIR EXT IX2 IX1 IX REL REL REL REL REL REL REL REL 24 2F 2E rr rr rr Bit Test Accumulator with Memory Byte (A) (M) ---- -- 2 A5 ii B5 dd 3 C5 hh ll 4 D5 ee ff 5 4 E5 ff 3 F5 25 23 2C 2B 2D 26 2A 20 01 03 05 07 09 0B 0D 0F 21 00 02 04 06 08 0A 0C 0E 10 12 14 16 18 1A 1C 1E rr rr rr rr rr rr rr rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd dd dd dd dd dd dd dd 3 3 3 3 3 3 3 3 5 5 5 5 5 5 5 5 3 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 Branch if Lower (Same as BCS) Branch if Lower or Same Branch if Interrupt Mask Clear Branch if Minus Branch if Interrupt Mask Set Branch if Not Equal Branch if Plus Branch Always PC (PC) + 2 + rel ? C = 1 PC (PC) + 2 + rel ? I = 0 PC (PC) + 2 + rel ? N = 1 PC (PC) + 2 + rel ? I = 1 PC (PC) + 2 + rel ? Z = 0 PC (PC) + 2 + rel ? N = 0 PC (PC) + 2 + rel ? 1 = 1 ---------- PC (PC) + 2 + rel ? C Z = 1 -- -- -- -- -- ---------- ---------- ---------- ---------- ---------- ---------- BRCLR n opr rel Branch if Bit n Clear PC (PC) + 2 + rel ? Mn = 0 DIR (b0) DIR (b1) DIR (b2) DIR (b3) -------- DIR (b4) DIR (b5) DIR (b6) DIR (b7) ---------- REL BRN rel Branch Never PC (PC) + 2 + rel ? 1 = 0 BRSET n opr rel Branch if Bit n Set PC (PC) + 2 + rel ? Mn = 1 DIR (b0) DIR (b1) DIR (b2) DIR (b3) -------- DIR (b4) DIR (b5) DIR (b6) DIR (b7) DIR (b0) DIR (b1) DIR (b2) DIR (b3) ---------- DIR (b4) DIR (b5) DIR (b6) DIR (b7) BSET n opr Set Bit n Mn 1 BSR rel Branch to Subroutine PC (PC) + 2; push (PCL) SP (SP) - 1; push (PCH) SP (SP) - 1 PC (PC) + rel ---------- REL AD rr Technical Data 114 MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 Instruction Set MOTOROLA Cycles 3 3 3 6 Effect on CCR Operand Address Mode Instruction Set Instruction Set Summary Table 12-6. Instruction Set Summary (Sheet 3 of 6) Opcode Source Form CLC CLI CLR opr CLRA CLRX CLR opr,X CLR ,X CMP #opr CMP opr CMP opr CMP opr,X CMP opr,X CMP ,X COM opr COMA COMX COM opr,X COM ,X CPX #opr CPX opr CPX opr CPX opr,X CPX opr,X CPX ,X DEC opr DECA DECX DEC opr,X DEC ,X EOR #opr EOR opr EOR opr EOR opr,X EOR opr,X EOR ,X INC opr INCA INCX INC opr,X INC ,X JMP opr JMP opr JMP opr,X JMP opr,X JMP ,X Clear Carry Bit Clear Interrupt Mask Operation Description C0 I0 M $00 A $00 X $00 M $00 M $00 H I NZC -------- 0 -- 0 ------ INH INH DIR INH INH IX1 IX IMM DIR EXT IX2 IX1 IX DIR INH INH IX1 IX IMM DIR EXT IX2 IX1 IX DIR INH INH IX1 IX IMM DIR EXT IX2 IX1 IX DIR INH INH IX1 IX DIR EXT IX2 IX1 IX 98 9A 3F 4F 5F 6F 7F dd Clear Byte ---- 0 1 -- ff Compare Accumulator with Memory Byte (A) - (M) ---- 2 A1 ii B1 dd 3 C1 hh ll 4 D1 ee ff 5 4 E1 ff 3 F1 33 43 53 63 73 dd 5 3 3 6 5 Complement Byte (One's Complement) M (M) = $FF - (M) A (A) = $FF - (A) X (X) = $FF - (X) M (M) = $FF - (M) M (M) = $FF - (M) ---- 1 ff Compare Index Register with Memory Byte (X) - (M) ---- 2 A3 ii B3 dd 3 C3 hh ll 4 D3 ee ff 5 4 E3 ff 3 F3 3A 4A 5A 6A 7A dd 5 3 3 6 5 Decrement Byte M (M) - 1 A (A) - 1 X (X) - 1 M (M) - 1 M (M) - 1 ---- -- ff EXCLUSIVE OR Accumulator with Memory Byte A (A) (M) ---- -- 2 A8 ii B8 dd 3 C8 hh ll 4 D8 ee ff 5 4 E8 ff 3 F8 3C 4C 5C 6C 7C dd 5 3 3 6 5 Increment Byte M (M) + 1 A (A) + 1 X (X) + 1 M (M) + 1 M (M) + 1 ---- -- ff Unconditional Jump PC Jump Address ---------- BC dd 2 CC hh ll 3 DC ee ff 4 3 EC ff 2 FC MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 MOTOROLA Instruction Set Technical Data 115 Cycles 2 2 5 3 3 6 5 Effect on CCR Operand Address Mode Instruction Set Table 12-6. Instruction Set Summary (Sheet 4 of 6) Opcode Source Form JSR opr JSR opr JSR opr,X JSR opr,X JSR ,X LDA #opr LDA opr LDA opr LDA opr,X LDA opr,X LDA ,X LDX #opr LDX opr LDX opr LDX opr,X LDX opr,X LDX ,X LSL opr LSLA LSLX LSL opr,X LSL ,X LSR opr LSRA LSRX LSR opr,X LSR ,X MUL NEG opr NEGA NEGX NEG opr,X NEG ,X NOP ORA #opr ORA opr ORA opr ORA opr,X ORA opr,X ORA ,X ROL opr ROLA ROLX ROL opr,X ROL ,X Operation Description H I NZC PC (PC) + n (n = 1, 2, or 3) Push (PCL); SP (SP) - 1 Push (PCH); SP (SP) - 1 PC Effective Address Jump to Subroutine ---------- DIR EXT IX2 IX1 IX IMM DIR EXT IX2 IX1 IX IMM DIR EXT IX2 IX1 IX DIR INH INH IX1 IX DIR INH INH IX1 IX INH DIR INH INH IX1 IX INH IMM DIR EXT IX2 IX1 IX DIR INH INH IX1 IX BD dd 5 CD hh ll 6 DD ee ff 7 6 ED ff 5 FD 2 A6 ii B6 dd 3 C6 hh ll 4 D6 ee ff 5 4 E6 ff 3 F6 2 AE ii BE dd 3 CE hh ll 4 DE ee ff 5 4 EE ff 3 FE 38 48 58 68 78 34 44 54 64 74 42 30 40 50 60 70 9D dd dd 5 3 3 6 5 5 3 3 6 5 1 1 5 3 3 6 5 2 Load Accumulator with Memory Byte A (M) ---- -- Load Index Register with Memory Byte X (M) ---- -- Logical Shift Left (Same as ASL) C b7 b0 0 ---- ff dd Logical Shift Right 0 b7 b0 C ---- 0 ff Unsigned Multiply X : A (X) x (A) M -(M) = $00 - (M) A -(A) = $00 - (A) X -(X) = $00 - (X) M -(M) = $00 - (M) M -(M) = $00 - (M) 0 ------ 0 Negate Byte (Two's Complement) ---- ff No Operation ---------- Logical OR Accumulator with Memory A (A) (M) ---- -- 2 AA ii BA dd 3 CA hh ll 4 DA ee ff 5 4 EA ff 3 FA 39 49 59 69 79 dd 5 3 3 6 5 Rotate Byte Left through Carry Bit C b7 b0 ---- ff Technical Data 116 MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 Instruction Set MOTOROLA Cycles Effect on CCR Operand Address Mode Instruction Set Instruction Set Summary Table 12-6. Instruction Set Summary (Sheet 5 of 6) Opcode Source Form ROR opr RORA RORX ROR opr,X ROR ,X RSP Operation Description H I NZC Rotate Byte Right through Carry Bit b7 b0 C ---- DIR INH INH IX1 IX INH 36 46 56 66 76 9C dd ff Reset Stack Pointer SP $00FF SP (SP) + 1; Pull (CCR) SP (SP) + 1; Pull (A) SP (SP) + 1; Pull (X) SP (SP) + 1; Pull (PCH) SP (SP) + 1; Pull (PCL) SP (SP) + 1; Pull (PCH) SP (SP) + 1; Pull (PCL) ---------- RTI Return from Interrupt INH 80 RTS SBC #opr SBC opr SBC opr SBC opr,X SBC opr,X SBC ,X SEC SEI STA opr STA opr STA opr,X STA opr,X STA ,X STOP STX opr STX opr STX opr,X STX opr,X STX ,X SUB #opr SUB opr SUB opr SUB opr,X SUB opr,X SUB ,X Return from Subroutine ---------- INH IMM DIR EXT IX2 IX1 IX INH INH DIR EXT IX2 IX1 IX INH DIR EXT IX2 IX1 IX IMM DIR EXT IX2 IX1 IX 81 Subtract Memory Byte and Carry Bit from Accumulator A (A) - (M) - (C) ---- 2 A2 ii B2 dd 3 C2 hh ll 4 D2 ee ff 5 4 E2 ff 3 F2 99 9B 2 2 Set Carry Bit Set Interrupt Mask C1 I1 -------- 1 -- 1 ------ Store Accumulator in Memory M (A) ---- -- B7 dd 4 C7 hh ll 5 D7 ee ff 6 5 E7 ff 4 F7 8E 2 Stop Oscillator and Enable IRQ Pin -- 0 ------ Store Index Register In Memory M (X) ---- -- BF dd 4 CF hh ll 5 DF ee ff 6 5 EF ff 4 FF 2 A0 ii B0 dd 3 C0 hh ll 4 D0 ee ff 5 4 E0 ff 3 F0 Subtract Memory Byte from Accumulator A (A) - (M) ---- SWI Software Interrupt PC (PC) + 1; Push (PCL) SP (SP) - 1; Push (PCH) SP (SP) - 1; Push (X) SP (SP) - 1; Push (A) -- 1 ------ SP (SP) - 1; Push (CCR) SP (SP) - 1; I 1 PCH Interrupt Vector High Byte PCL Interrupt Vector Low Byte INH 83 MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 MOTOROLA Instruction Set Technical Data 117 Cycles 5 3 3 6 5 2 9 6 1 0 Effect on CCR Operand Address Mode Instruction Set Table 12-6. Instruction Set Summary (Sheet 6 of 6) Opcode Source Form TAX TST opr TSTA TSTX TST opr,X TST ,X TXA WAIT A C CCR dd dd rr DIR ee ff EXT ff H hh ll I ii IMM INH IX IX1 IX2 M N n Operation Transfer Accumulator to Index Register Description X (A) H I NZC ---------- INH DIR INH INH IX1 IX INH INH 97 3D 4D 5D 6D 7D 9F 8F dd Test Memory Byte for Negative or Zero (M) - $00 ---- -- ff Transfer Index Register to Accumulator Stop CPU Clock and Enable Interrupts Accumulator Carry/borrow flag Condition code register Direct address of operand Direct address of operand and relative offset of branch instruction Direct addressing mode High and low bytes of offset in indexed, 16-bit offset addressing Extended addressing mode Offset byte in indexed, 8-bit offset addressing Half-carry flag High and low bytes of operand address in extended addressing Interrupt mask Immediate operand byte Immediate addressing mode Inherent addressing mode Indexed, no offset addressing mode Indexed, 8-bit offset addressing mode Indexed, 16-bit offset addressing mode Memory location Negative flag Any bit A (X) ---------- -- 0 ------ opr PC PCH PCL REL rel rr SP X Z # () -( ) ? : -- Operand (one or two bytes) Program counter Program counter high byte Program counter low byte Relative addressing mode Relative program counter offset byte Relative program counter offset byte Stack pointer Index register Zero flag Immediate value Logical AND Logical OR Logical EXCLUSIVE OR Contents of Negation (two's complement) Loaded with If Concatenated with Set or cleared Not affected 12.6 Opcode Map See Table 12-7. Technical Data 118 MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 Instruction Set MOTOROLA Cycles 2 4 3 3 5 4 2 2 Effect on CCR Operand Address Mode Table 12-7. Opcode Map Bit Manipulation DIR MSB LSB MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 Technical Data MOTOROLA Instruction Set 119 Branch REL 2 DIR 3 Read-Modify-Write INH 4 INH 5 IX1 6 IX 7 Control INH 8 9 RTI INH 6 RTS INH Register/Memory IMM A 2 SUB IMM 2 2 CMP IMM 2 2 SBC IMM 2 2 CPX IMM 2 2 AND IMM 2 2 BIT IMM 2 2 LDA IMM 2 2 2 EOR IMM 2 2 ADC IMM 2 2 ORA IMM 2 2 ADD IMM 2 2 DIR 1 INH 9 DIR B 3 SUB DIR 3 3 CMP DIR 3 3 SBC DIR 3 3 CPX DIR 3 3 AND DIR 3 3 BIT DIR 3 3 LDA DIR 3 4 STA DIR 3 3 EOR DIR 3 3 ADC DIR 3 3 ORA DIR 3 3 ADD DIR 3 2 JMP DIR 3 5 JSR DIR 3 3 LDX DIR 3 4 STX DIR 3 EXT C 4 SUB EXT 3 4 CMP EXT 3 4 SBC EXT 3 4 CPX EXT 3 4 AND EXT 3 4 BIT EXT 3 4 LDA EXT 3 5 STA EXT 3 4 EOR EXT 3 4 ADC EXT 3 4 ORA EXT 3 4 ADD EXT 3 3 JMP EXT 3 6 JSR EXT 3 4 LDX EXT 3 5 STX EXT 3 IX2 D 5 SUB IX2 2 5 CMP IX2 2 5 SBC IX2 2 5 CPX IX2 2 5 AND IX2 2 5 BIT IX2 2 5 LDA IX2 2 6 STA IX2 2 5 EOR IX2 2 5 ADC IX2 2 5 ORA IX2 2 5 ADD IX2 2 4 JMP IX2 2 7 JSR IX2 2 5 LDX IX2 2 6 STX IX2 2 IX1 E 4 SUB IX1 1 4 CMP IX1 1 4 SBC IX1 1 4 CPX IX1 1 4 AND IX1 1 4 BIT IX1 1 4 LDA IX1 1 5 STA IX1 1 4 EOR IX1 1 4 ADC IX1 1 4 ORA IX1 1 4 ADD IX1 1 3 JMP IX1 1 6 JSR IX1 1 4 LDX IX1 1 5 STX IX1 1 IX F 3 SUB IX 3 CMP IX 3 SBC IX 3 CPX IX 3 AND IX 3 BIT IX 3 LDA IX 4 STA IX 3 EOR IX 3 ADC IX 3 ORA IX 3 ADD IX 2 JMP IX 5 JSR IX 3 LDX IX 4 STX IX MSB LSB 0 0 1 2 3 4 5 6 7 8 9 A B C D E F 5 5 3 5 3 3 6 5 BRSET0 BSET0 BRA NEG NEGA NEGX NEG NEG 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 5 5 3 BRCLR0 BCLR0 BRN 3 DIR 2 1 DIR 2 REL 5 5 3 11 BRSET1 BSET1 BHI MUL 3 DIR 2 DIR 2 REL 1 INH 5 5 3 5 3 3 6 5 BRCLR1 BCLR1 BLS COM COMA COMX COM COM 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 5 5 3 5 3 3 6 5 BRSET2 BSET2 BCC LSR LSRA LSRX LSR LSR 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 5 5 3 BRCLR2 BCLR2 BCS/BLO 3 DIR 2 DIR 2 REL 5 5 3 5 3 3 6 5 BRSET3 BSET3 BNE ROR RORA RORX ROR ROR 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 5 5 3 5 3 3 6 5 BRCLR3 BCLR3 BEQ ASR ASRA ASRX ASR ASR 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 5 5 3 5 3 3 6 5 BRSET4 BSET4 BHCC ASL/LSL ASLA/LSLA ASLX/LSLX ASL/LSL ASL/LSL 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 5 5 3 5 3 3 6 5 BRCLR4 BCLR4 BHCS ROL ROLA ROLX ROL ROL 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 5 5 3 5 3 3 6 5 BRSET5 BSET5 BPL DEC DECA DECX DEC DEC 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 5 5 3 BRCLR5 BCLR5 BMI 3 DIR 2 DIR 2 REL 5 5 3 5 3 3 6 5 BRSET6 BSET6 BMC INC INCA INCX INC INC 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 5 5 3 4 3 3 5 4 BRCLR6 BCLR6 BMS TST TSTA TSTX TST TST 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 5 5 3 BRSET7 BSET7 BIL 3 DIR 2 DIR 2 REL 1 5 5 3 5 3 3 6 5 BRCLR7 BCLR7 BIH CLR CLRA CLRX CLR CLR 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 0 1 2 3 4 5 6 7 8 9 A B C D E F 2 2 2 10 SWI INH 2 2 2 2 1 1 1 1 1 1 1 2 TAX INH 2 CLC INH 2 2 SEC INH 2 2 CLI INH 2 2 SEI INH 2 2 RSP INH 2 NOP INH 2 2 STOP INH 2 2 WAIT TXA INH 1 INH 6 BSR REL 2 2 LDX 2 IMM 2 2 MSB LSB INH = Inherent IMM = Immediate DIR = Direct EXT = Extended REL = Relative IX = Indexed, No Offset IX1 = Indexed, 8-Bit Offset IX2 = Indexed, 16-Bit Offset 0 MSB of Opcode in Hexadecimal Instruction Set Opcode Map LSB of Opcode in Hexadecimal 0 5 Number of Cycles BRSET0 Opcode Mnemonic 3 DIR Number of Bytes/Addressing Mode Instruction Set Technical Data 120 MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 Instruction Set MOTOROLA Technical Data -- MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A Section 13. Electrical Specifications 13.1 Contents 13.2 13.3 13.4 13.5 13.6 13.7 13.8 13.9 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122 Operating Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . 122 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Power Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 5.0-V DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . 125 3.3-V DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . 126 5.0-V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129 . . . . . . . . . . . . . . . 132 . . . . . . . . . . . . . . . 133 13.10 3.3-V Control Timing 13.11 5.0-V Serial Peripheral Interface Timing 13.12 3.3-V Serial Peripheral Interface Timing 13.2 Introduction This section contains the electrical and timing specifications. MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 MOTOROLA Electrical Specifications Technical Data 121 Electrical Specifications 13.3 Maximum Ratings mum Maximum ratings are the extreme limits to which the MCU can be exposed without permanently damaging it. The MCU contains circuitry to protect the inputs against damage from high static voltages; however, do not apply voltages higher than those shown in the table below. Keep VIn and VOut within the range VSS (VIn or VOut) VDD. Connect unused inputs to the appropriate voltage level, either VSS or VDD. Rating Supply voltage Current drain per pin excluding VDD and VSS IRQ pin only Symbol VDD I VIn Tstg Value -0.3 to +7.0 25 VSS -0.3 to 2 x VDD + 0.3 -65 to +150 Unit V mA V Storage temperature range C NOTE: This device is not guaranteed to operate properly at the maximum ratings. Refer to 13.7 5.0-V DC Electrical Characteristics and 13.8 3.3-V DC Electrical Characteristics for guaranteed operating conditions. 13.4 Operating Temperature Range Characteristic Operating temperature range(1) MC68HC05C8AP, FN, B, FB MC68HSC05C8CP, CFN, CB, CFB MC68HC05C8AVP, VN, VB, VFB MC68HC05C8AMP, MFN, MB, MFB 1. P = Plastic dual in-line package (PDIP) FN = Plastic-leaded chip carrier (PLCC) B = Shrink dual in-line-package (SDIP) FB = Quad flat pack (QFP) Symbol Value TL to TH 0 to +70 -40 to +85 -40 to +105 -40 to +125 Unit TA C Technical Data 122 MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 Electrical Specifications MOTOROLA Electrical Specifications Thermal Characteristics 13.5 Thermal Characteristics Characteristic Thermal resistance Plastic dual in-line package Plastic leaded chip carrier (PLCC) Quad flat pack (QFP0) Plastic shrink DIP (SDIP) Symbol Value 60 70 95 60 Unit JA C/W 13.6 Power Considerations The average chip-junction temperature, TJ, in C, can be obtained from: TJ = TA + (PD x JA) (1) where: TA = Ambient temperature, C JA = Package thermal resistance, junction to ambient, C/W. PD = PINT + PI/O PINT = IDD x VDD watts (chip internal power) PI/O = Power dissipation on input and output pins (user-determined) For most applications PI/O PINT and can be neglected. Following is an approximate relationship between PD and TJ (neglecting PI/O): PD = K / (TJ + 273 C) (2) Solving equations (1) and (2) for K gives: K = PD x (TA + 273 C) + JA x (PD)2 (3) where K is a constant pertaining to the particular part. K can be determined from equation (3) by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by solving equations (1) and (2) iteratively for any value of TA. MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 MOTOROLA Electrical Specifications Technical Data 123 Electrical Specifications VDD = 4.5 V VDD Pins PA7-PA0 PB7-PB0 PC7-PC0 PD5-PD0, PD7 R1 3.26 R2 2.38 C 50 pF TEST POINT R2 SEE TABLE C SEE TABLE R1 SEE TABLE VDD = 3.0 V Pins PA7-PA0 PB7-PB0 PC7-PC0 PD5-PD0, PD7 R1 10.91 R2 6.32 C 50 pF Figure 13-1. Test Load Technical Data 124 MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 Electrical Specifications MOTOROLA Electrical Specifications 5.0-V DC Electrical Characteristics 13.7 5.0-V DC Electrical Characteristics Characteristic(1) Output voltage ILoad = 10.0 A ILoad = -10.0 A Output high voltage (ILoad = -0.8 mA) PA7-PA0, PB7-PB0, PC6-PC0, TCMP (ILoad = -1.6 mA) PD4-PD1 (ILoad = -5.0 mA) PC7 Output low voltage (ILoad = 1.6 mA) PA7-PA0, PB7-PB0, PC6-PC0, PD4-PD1, TCMP (ILoad = 10 mA) PC7 Input high voltage PA7-PA0, PB7-PB0, PC7-PC0, PD7, PD5-PD0, TCAP, IRQ, RESET, OSC1 Input low voltage PA7-PA0, PB7-PB0, PC7-PC0, PD7, PD5-PD0, TCAP, IRQ, RESET, OSC1 Supply current (4.5-5.5 Vdc @ fBus = 2.1 MHz) Run(3) Wait(4) Stop(5) 25C 0C to 70C (standard) -40C to +125C (standard) I/O ports hi-z leakage current PA7-PA0, PB7-PB0 (without pullup) PC7-PC0, PD7, PD5-PD0 Input current RESET, IRQ, OSC1, TCAP, PD7, PD5-PD0 Input pullup current(6) PB7-PB0 (with pullup) Capacitance Ports (as input or output) RESET, IRQ, OSC1, TCAP, PD7, PD5, PD0 Symbol VOL VOH Min -- VDD-0.1 VDD-0.8 VDD-0.8 VDD-0.8 -- -- 0.7xVDD Typ(2) -- -- -- -- -- Max 0.1 -- -- -- -- Unit V VOH V VOL -- -- -- 0.4 0.4 VDD V VIH V VIL VSS -- 0.2xVDD V -- -- IDD -- -- -- IOZ IIn IIn COut CIn -- -- 175 3.50 1.00 1 -- -- -- -- 385 5.25 3.25 20 40 50 mA mA A A A A A A 10 1 750 -- -- -- -- 12 8 pF 1. VDD = 5.0 Vdc 10%, VSS = 0 Vdc, TA = -40C to +125C, unless otherwise noted. 2. Typical values reflect measurements taken on average processed devices at the midpoint of voltage range, 25C only. 3. Run (operating) IDD measured using external square wave clock source; all I/O pins configured as inputs, Port B = VDD, all other inputs VIL = 0.2 V, VIH = VDD-0.2 V; no DC loads; less than 50 pF on all outputs; CL = 20 pF on OSC2. 4. Wait IDD measured using external square wave clock source; all I/O pins configured as inputs, Port B = VDD, all other inputs VIL = 0.2 V, VIH = VDD-0.2 V; no DC loads; less than 50 pF on all outputs; CL = 20 pF on OSC2. Wait IDD is affected linearly by the OSC2 capacitance. 5. Stop IDD measured with OSC1 = 0.2 V; all I/O pins configured as inputs, Port B = VDD, all other inputs VIL = 0.2 V, VIH = VDD -0.2 V. 6. Input pullup current measured with VIL = 0.2 V. MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 MOTOROLA Electrical Specifications Technical Data 125 Electrical Specifications 13.8 3.3-V DC Electrical Characteristics Characteristic(1) Output voltage ILoad = 10.0 A ILoad = -10.0 A Output high voltage (ILoad = -0.2 mA) PA7-PA0, PB7-PB0, PC6-PC0, TCMP (ILoad = -0.4 mA) PD4-PD1 (ILoad = -1.5 mA) PC7 Output low voltage (ILoad = 0.4 mA) PA7-PA0, PB7-PB0, PC6-PC0, PD4-PD1, TCMP (ILoad = 6 mA) PC7 Input high voltage PA7-PA0, PB7-PB0, PC7-PC0, PD7, PD5-PD0, TCAP, IRQ, RESET, OSC1 Input low voltage PA7-PA0, PB7-PB0, PC7-PC0, PD7, PD5-PD0, TCAP, IRQ, RESET, OSC1 Supply current (3.0-3.6 Vdc @ fBus = 1.0 MHz) Run(3) Wait(4) Stop(5) 25C 0C to +70C (standard) -40C to +125C (standard) I/O ports hi-z leakage current PA7-PA0, PB7-PB0 (without pullup) PC7-PC0, PD7, PD5-PD0 Input current RESET, IRQ, OSC1, TCAP, PD7, PD5, PD0 Input pullup current(6) PB7-PB0 (with pullup) Capacitance Ports (as input or output) RESET, IRQ, OSC1, TCAP, PD7, PD5, PD0 -- -- IDD -- -- -- IOZ IIn IIn COut CIn -- -- 75 -- -- 1 -- -- -- -- 175 -- -- 8 16 20 1.00 500 1.60 900 mA A Symbol VOL VOH Min -- VDD-0.1 VDD-0.3 VDD-0.3 VDD-0.3 Typ(2) -- -- -- -- -- Max 0.1 -- -- -- -- Unit V VOH V VOL -- -- 0.7xVDD -- -- 0.3 0.3 VDD V VIH -- V VIL VSS -- 0.2xVDD V A A A A A A pF 10 1 350 12 8 1. VDD = 3.3 Vdc 0.3 Vdc, VSS = 0 Vdc, TA = -40C to +125C, unless otherwise noted. 2. Typical values reflect measurements taken on average processed devices at the midpoint of voltage range, 25C only. 3. Run (operating) IDD measured using external square wave clock source; all I/O pins configured as inputs, Port B = VDD, all other inputs VIL = 0.2 V, VIH = VDD -0.2 V; no DC loads; less than 50 pF on all outputs; CL = 20 pF on OSC2. 4. Wait IDD measured using external square wave clock source; all I/O pins configured as inputs, Port B = VDD, all other inputs VIL = 0.2 V, VIH = VDD -0.2 V; no DC loads; less than 50 pF on all outputs; CL = 20 pF on OSC2. Wait IDD is affected linearly by the OSC2 capacitance. 5. Stop IDD measured with OSC1 = 0.2 V; all I/O pins configured as inputs, Port B = VDD, all other inputs VIL = 0.2 V, VIH = VDD -0.2 V. 6. Input pullup current measured with VIL = 0.2 V. Technical Data 126 MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 Electrical Specifications MOTOROLA Electrical Specifications 3.3-V DC Electrical Characteristics 5.00 mA VDD = 5.5 V T = -40C TO 125C SUPPLY CURRENT (IDD) 4.00 mA N RU P (O IN AT ER ID G) D 3.00 mA IT WA I DD 2.00 mA 1.00 mA 50 A 0.5 MHz 1.0 MHz 1.5 MHz STOP IDD (MHZ) 2.0 MHz INTERNAL CLOCK FREQUENCY (XTAL / 2) Figure 13-2. Maximum Supply Current versus Internal Clock Frequency, VDD = 5.5 V 1.50 mA VDD = 3.6 V T = -40C TO 125C SUPPLY CURRENT (IDD) 1.00 mA RU N ( OP TID AI W ER AT IN D 500 mA STOP IDD 0.5 MHz 1.0 MHz INTERNAL CLOCK FREQUENCY (XTAL / 2) Figure 13-3. Maximum Supply Current versus Internal Clock Frequency, VDD = 3.6 V MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 MOTOROLA Electrical Specifications G) ID D Technical Data 127 Electrical Specifications 13.9 5.0-V Control Timing Characteristic(1) Oscillator frequency Crystal External clock Internal operating frequency Crystal External clock Internal clock cycle time Crystal oscillator startup time Stop recovery startup time (crystal oscillator) RESET pulse width Timer Resolution(2) Input capture pulse width Input capture pulse period Interrupt pulse width low (edge-triggered) Interrupt pulse period OSC1 pulse width tRESL tTH, tTL tTLTL tILIH tILIL tOH, tOL 4.0 125 Note(3) 125 Note(4) 90 -- -- -- -- -- -- tCYC ns tCYC ns tCYC ns Symbol fOSC Min -- dc -- dc 480 -- -- Max 4.2 4.2 2.1 2.1 -- 100 100 -- Unit MHz fOP tCYC tOXOV tILCH tRL MHz ns ms ms tCYC 1.5 1. VDD = 5.0 Vdc 10%, VSS = 0 Vdc, TA = -40C to +125C, unless otherwise noted. 2. Because a 2-bit prescaler in the timer must count four internal cycles (tCYC), this is the limiting minimum factor in determining the timer resolution. 3. The minimum period tTLTL should not be less than the number of cycle times it takes to execute the capture interrupt service routine plus 24 tCYC. 4. The minimum tILIL should not be less than the number of cycle times it takes to execute the interrupt service routine plus 19 tCYc. Technical Data 128 MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 Electrical Specifications MOTOROLA Electrical Specifications 3.3-V Control Timing 13.10 3.3-V Control Timing Characteristic(1) Oscillator frequency Crystal External clock Internal operating frequency Crystal External clock Internal clock cycle time Crystal oscillator startup time Stop recovery startup time (crystal oscillator) RESET pulse width Timer Resolution(2) Input capture pulse width Input capture pulse period Interrupt pulse width low (edge-triggered) Interrupt pulse period OSC1 pulse width tRESL tTH, tTL tTLTL tILIH tILIL tOH, tOL 4.0 250 Note(3) 250 Note(4) 200 -- -- -- -- -- -- tCYC ns tCYC ns tCYC ns Symbol fOSC Min -- dc -- dc 1000 Max 2.0 2.0 1.00 1.00 -- 100 100 1.5 -- Unit MHz fOP tCYC tOXOV tILCH tRL MHz ns ms ms tCYC 1. VDD = 3.3 Vdc 0.3 Vdc, VSS = 0 Vdc, TA = -40C to +125C, unless otherwise noted. 2. Because a 2-bit prescaler in the timer must count four internal cycles (tCYC), this is the limiting minimum factor in determining the timer resolution. 3. The minimum period tTLTL should not be less than the number of cycle times it takes to execute the capture interrupt service routine plus 24 tCYC. 4. The minimum tILIL should not be less than the number of cycle times it takes to execute the interrupt service routine plus 19 tCYC. tTLTL TCAP PIN tTH tTL Figure 13-4. TCAP Timing Relationships MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 MOTOROLA Electrical Specifications Technical Data 129 Electrical Specifications tILIL IRQ PIN tILIH a. Edge-Sensitive Trigger Condition. The minimum pulse width (tILIH) is either 125 ns (fOP = 2.1 MHz) or 250 ns (fOP = 1 MHz). The period tILIL should not be less than the number of tCYC cycles it takes to execute the interrupt service routine plus 19 tCYC cycles. IRQ1 NORMALLY USED WITH WIRED-OR CONNECTION . . . tILIH IRQn IRQ (INTERNAL) b. Level-Sensitive Trigger Condition. If after servicing an interrupt the IRQ remains low, the next interrupt is recognized. Figure 13-5. External Interrupt Timing INTERNAL CLOCK(1) INTERNAL ADDRESS BUS(1) 1FFE 1FFE 1FFE 1FFE 1FFF NEW PC INTERNAL DATA BUS(1) RESET(2) tRL NEW PCH NEW PCL OP CODE Notes: 1. Internal clock, internal address bus, and internal data bus are not available externally. 2. The next rising edge of the internal clock after the rising edge of RESET initiates the reset sequence. Figure 13-6. External Reset Timing Technical Data 130 MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 Electrical Specifications MOTOROLA Electrical Specifications 3.3-V Control Timing OSC(1) tRL RESET tILIH IRQ(2) 4064 tCYC IRQ(3) INTERNAL CLOCK INTERNAL ADDRESS BUS 1FFE 1FFE 1FFE 1FFE 1FFE 1FFF(4) Notes: 1. Represents the internal clocking of the OSC1 pin 2. IRQ pin edge-sensitive mask option 3. IRQ pin level- and edge-sensitive mask option 4. RESET vector address shown for timing example RESET OR INTERRUPT VECTOR FETCH Figure 13-7. STOP Recovery Timing Diagram (NOTE 1) VDD OSC1 PIN(2) 4064 tCYC INTERNAL CLOCK(3) INTERNAL ADDRESS BUS(3) 1FFE 1FFE 1FFE 1FFE 1FFE 1FFE 1FFF INTERNAL DATA BUS(3) NOTES: 1. Power-on reset threshold is typically between 1 V and 2 V. 2. OSC1 line is meant to represent time only, not frequency. 3. Internal clock, internal address bus, and internal data bus are not available externally. NEW PCH NEW PCL Figure 13-8. Power-On Reset Timing Diagram MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 MOTOROLA Electrical Specifications Technical Data 131 Electrical Specifications 13.11 5.0-V Serial Peripheral Interface Timing Num Characteristic(1) Operating frequency Master Slave 1 Cycle time Master Slave Enable lead time Master Slave Enable lag time Master Slave Clock (SCK) high time Master Slave Clock (SCK) low time Master Slave Data setup time (inputs) Master Slave Data hold time (inputs) Master Slave Slave access time (time-to-data active from highimpedance state) Slave disable time (hold time to high-impedance state) Data valid Master (before capture edge) Slave (after enable edge)(3) Data hold time (outputs) Master (after capture edge) Slave (after enable edge) Rise time (20% VDD to 70% VDD, CL = 200 pF) SPI outputs (SCK, MOSI, and MISO) SPI inputs (SCK, MOSI, MISO, and SS) Fall time (70% VDD to 20% VDD, CL = 200 pF) SPI outputs (SCK, MOSI, and MISO) SPI inputs (SCK, MOSI, MISO, and SS) Symbol fOP(M) fOP(S) tCYC(M) tCYC(S) tLead(M) tLead(S) tLag(M) tLag(S) tW(SCKH)M tW(SCKH)S tW(SCKL)M tW(SCKL)S tSU(M) tSU(S) tH(M) tH(S) tA tDIS tV(M) tV(S) tHO(M) tHO(S) tRM tRS tFM tFS Min dc dc 2.0 480 (2) Max 0.5 2.1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 120 240 -- 240 -- -- 100 2.0 100 2.0 Unit fOP MHz tCYC ns ns 2 240 (2) 3 ns 720 340 190 340 190 100 100 100 100 0 -- 0.25 -- 0.25 0 -- -- -- -- 4 ns 5 ns 6 ns 7 8 9 10 ns ns ns tCYC(M) ns tCYC(M) ns ns s ns s 11 12 13 1. VDD = 5.0 Vdc 10%; VSS = 0 Vdc, TA = TL to TH. Refer to Figure 13-9 and Figure 13-10 for timing diagrams. 2. Signal production depends on software. 3. Assumes 200 pF load on all SPI pins Technical Data 132 MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 Electrical Specifications MOTOROLA Electrical Specifications 3.3-V Serial Peripheral Interface Timing 13.12 3.3-V Serial Peripheral Interface Timing Num Operating frequency Master Slave 1 Cycle time Master Slave Enable lead time Master Slave Enable lag time Master Slave Clock (SCK) high time Master Slave Clock (SCK) low time Master Slave Data setup time (inputs) Master Slave Data hold time (inputs) Master Slave Slave access time (time to data active from high-impedance state) Slave disable time (hold time to high-impedance state) Data valid Master (before capture edge) Slave (after enable edge)(3) Data hold time (outputs) Master (after capture edge) Slave (after enable edge) Rise time (20% VDD to 70% VDD, CL = 200 pF) SPI outputs (SCK, MOSI, and MISO) SPI Inputs (SCK, MOSI, MISO, and SS) Fall time (70% VDD to 20% VDD, CL = 200 pF) SPI outputs (SCK, MOSI, and MISO) SPI inputs (SCK, MOSI, MISO, and SS) Characteristic(1) Symbol fOP(M) fOP(S) tCYC(M) tCYC(S) tLead(M) tLead(S) tLag(M) tLag(S) tW(SCKH)M tW(SCKH)S tW(SCKL)M tW(SCKL)S tSU(M) tSU(S) tH(M) tH(S) tA tDIS tV(M) tV(S) tHO(M) tHO(S) tRM tRS tFM tFS Min dc dc 2.0 1.0 (2) Max 0.5 1.0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 250 500 -- 500 -- -- 200 2.0 200 2.0 Unit fOP MHz tCYC s ns 2 500 (2) 3 1.5 720 400 720 400 200 200 200 200 0 -- 0.25 -- 0.25 0 -- -- -- -- ns s ns 4 5 ns 6 ns 7 8 9 10 ns ns ns tCYC(M) ns tCYC(M) ns ns s ns s 11 12 13 1. VDD = 3.3 Vdc 0.3 Vdc; VSS = 0 Vdc, TA = TL to TH. Refer to Figure 13-9 and Figure 13-10 for timing diagrams. 2. Signal production depends on software. 3. Assumes 200 pF load on all SPI pins MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 MOTOROLA Electrical Specifications Technical Data 133 Electrical Specifications SS (INPUT) SS PIN OF MASTER HELD HIGH. 1 12 5 4 12 13 13 12 SCK (CPOL = 0) (OUTPUT) NOTE SCK (CPOL = 1) (OUTPUT) NOTE 5 4 6 7 LSB IN 10 BITS 6-1 11 (REF) MASTER LSB OUT 12 MISO (INPUT) 10 (REF) MOSI (OUTPUT) 13 MSB IN 11 MASTER MSB OUT BITS 6-1 Note: This first clock edge is generated internally, but is not seen at the SCK pin. a) SPI Master Timing (CPHA = 0) SS (INPUT) SS PIN OF MASTER HELD HIGH. 1 13 5 4 12 13 NOTE 6 7 LSB IN 10 BITS 6-1 11 MASTER LSB OUT 12 12 NOTE SCK (CPOL = 0) (OUTPUT) SCK (CPOL = 1) (OUTPUT) 5 4 MISO (INPUT) 10 (REF) MOSI (OUTPUT) 13 MSB IN 11 MASTER MSB OUT BITS 6-1 Note: This last clock edge is generated internally, but is not seen at the SCK pin. b) SPI Master Timing (CPHA = 1) Figure 13-9. SPI Master Timing Diagram Technical Data 134 MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 Electrical Specifications MOTOROLA Electrical Specifications 3.3-V Serial Peripheral Interface Timing SS (INPUT) 1 SCK (CPOL = 0) (INPUT) 2 SCK (CPOL = 1) (INPUT) 8 MISO (INPUT) SLAVE 6 MOSI (OUTPUT) MSB IN MSB OUT 7 10 BITS 6-1 BITS 6-1 11 LSB IN 5 4 12 13 SLAVE LSB OUT 11 9 NOTE 5 4 13 12 3 Note: Not defined but normally MSB of character just received. a) SPI Slave Timing (CPHA = 0) SS (INPUT) 1 SCK (CPOL = 0) (INPUT) 2 SCK (CPOL = 1) (INPUT) 8 MISO (OUTPUT) 5 4 10 NOTE SLAVE 6 MOSI (INPUT) MSB IN MSB OUT 7 10 BITS 6-1 12 BITS 6-1 11 LSB IN 13 9 SLAVE LSB OUT 5 4 3 13 12 Note: Not defined but normally LSB of character previously transmitted. b) SPI Slave Timing (CPHA = 1) Figure 13-10. SPI Slave Timing Diagram MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 MOTOROLA Electrical Specifications Technical Data 135 Electrical Specifications Technical Data 136 MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 Electrical Specifications MOTOROLA Technical Data -- MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A A Section 14. Mechanical Specifications 14.1 Contents 14.2 14.3 14.4 14.5 14.6 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 40-Pin Plastic Dual In-Line (DIP) Package (Case 711-03). . . . . . . . . . . . . . . . . . . . . . . . . . .138 42-Pin Plastic Shrink Dual In-Line (SDIP) Package (Case 858-01). . . . . . . . . . . . . . . . . . . . . . . . . . .138 44-Lead Plastic Leaded Chip Carrier (PLCC) (Case 777-02). . . . . . . . . . . . . . . . . . . . . . 139 44-Lead Quad Flat Pack (QFP) (Case 824A-01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 14.2 Introduction This section describes the dimensions of the: * * * * Dual in-line package (DIP) Plastic shrink dual in-line package (SDIP) Plastic leaded chip carrier (PLCC) Quad flat pack (QFP) MCU packages MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 MOTOROLA Mechanical Specifications Technical Data 137 Mechanical Specifications 14.3 40-Pin Plastic Dual In-Line (DIP) Package (Case 711-03) kage NOTES: 1. POSITION TOLERANCE OF LEADS (D), SHALL BEWITHIN 0.25 (0.010) AT MAXIMUM MATERIAL CONDITIONS, IN RELATION TO SEATING PLANE AND EACH OTHER. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSION B DOES NOT INCLUDE MOLD FLASH. MILLIMETERS MIN MAX 51.69 52.45 13.72 14.22 3.94 5.08 0.36 0.56 1.02 1.52 2.54 BSC 1.65 2.16 0.20 0.38 2.92 3.43 15.24 BSC 1 0 0.51 1.02 INCHES MIN MAX 2.035 2.065 0.540 0.560 0.155 0.200 0.014 0.022 0.040 0.060 0.100 BSC 0.065 0.085 0.008 0.015 0.115 0.135 0.600 BSC 0 1 0.020 0.040 40 21 B 1 20 A C N L J H G F D K SEATING PLANE M DIM A B C D F G H J K L M N 14.4 42-Pin Plastic Shrink Dual In-Line (SDIP) Package (Case 858-01) -A42 22 NOTES: 1. DIMENSIONS AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSIONS A AND B DO NOT INCLUDE MOLD FLASH. MAXIMUM MOLD FLASH 0.25 (0.010). -B1 21 L C H -TSEATING PLANE F D 42 PL 0.25 (0.010) M G TA S N K J 42 PL 0.25 (0.010) M M TB S DIM A B C D F G H J K L M N INCHES MIN MAX 1.435 1.465 0.540 0.560 0.155 0.200 0.014 0.022 0.032 0.046 0.070 BSC 0.300 BSC 0.008 0.015 0.115 0.135 0.600 BSC 0 15 0.020 0.040 MILLIMETERS MIN MAX 36.45 37.21 13.72 14.22 3.94 5.08 0.36 0.56 0.81 1.17 1.778 BSC 7.62 BSC 0.20 0.38 2.92 3.43 15.24 BSC 0 15 0.51 1.02 Technical Data 138 MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 Mechanical Specifications MOTOROLA Mechanical Specifications 44-Lead Plastic Leaded Chip Carrier (PLCC) (Case 777-02) 14.5 44-Lead Plastic Leaded Chip Carrier (PLCC) (Case 777-02) B 0.007(0.180) M T U L-M S N S L-M S N S -N- Y BRK D 0.007(0.180) M T Z -L-M- V 44 1 W D X VIEW D-D G1 0.010 (0.25) S T L-M S N S A R Z 0.007(0.180) M T 0.007(0.180) M T L-M S N S L-M S N S H 0.007(0.180) M T L-M S N S J E C G G1 0.010 (0.25) S T L-M S N S 0.004 (0.10) -TVIEW S SEATING PLANE K K1 F 0.007(0.180)M T VIEW S L-M S N S NOTES: 1. DATUMS -L-, -M-, AND -N- ARE DETERMINED WHERE TOP OF LEAD SHOLDERS EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIMENSION G1, TRUE POSITION TO BE MEASURED AT DATUM -T-, SEATING PLANE. 3. DIMENSION R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.25) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DIMENSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF THE MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMINSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTUSION(S) SHALL NOT CAUSE THE H DIMINSION TO BE GREATER THAN 0.037 (0.940140). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMINISION TO SMALLER THAN 0.025 (0.635). INCHES DIM A B C E F G H J K R U V W X Y Z G1 K1 MIN MAX 0.685 0.695 0.685 0.695 0.165 0.180 0.090 0.110 0.013 0.019 0.050 BSC 0.026 0.032 0.020 0.025 0.650 0.656 0.650 0.656 0.042 0.048 0.042 0.048 0.042 0.056 0.020 2 10 0.610 0.630 0.040 MILLIMETERS MIN MAX 17.40 17.65 17.40 17.65 4.20 4.57 2.29 2.79 0.33 0.48 1.27 BSC 0.66 0.81 0.51 0.64 16.51 16.66 16.51 16.66 1.07 1.21 1.07 1.21 1.07 1.42 0.50 2 10 15.50 16.00 1.02 MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 MOTOROLA Mechanical Specifications Technical Data 139 Mechanical Specifications 14.6 44-Lead Quad Flat Pack (QFP) (Case 824A-01) 6 L 33 34 23 22 S S D D B -A,B,DB S 0.20 (0.008) M C A-B 0.05 (0.002) A-B -AL -BB V DETAIL A 44 1 11 12 0.20 (0.008) M H A-B S DETAIL A F -DA 0.20 (0.008) M C A-B 0.05 (0.002) A-B S 0.20 (0.008) M H A-B BASE METAL S D S J S N D D S M DETAIL C DATUM PLANE 0.20 (0.008) M C A-B S D S SECTION B-B CE -CSEATING PLANE -HH 0.01 (0.004) G M M NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE H IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS A , B AND D TO BE DETERMINED AT DATUM PLANE H . 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE C . 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE H . 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. DIM A B C D E F G H J K L M N Q R S T U V W X MILLIMETERS MIN MAX 9.90 10.10 9.90 10.10 2.45 2.10 0.45 0.30 2.10 2.00 0.40 0.30 0.80 BSC 0.25 0.23 0.13 0.95 0.65 8.00 REF 10 5 0.17 0.13 7 0 0.30 0.13 12.95 13.45 0.13 0 12.95 13.45 0.40 1.6 REF INCHES MIN MAX 0.390 0.398 0.390 0.398 0.083 0.096 0.012 0.018 0.079 0.083 0.012 0.016 0.031 BSC 0.010 0.005 0.009 0.026 0.037 0.315 REF 10 5 0.005 0.007 7 0 0.005 0.012 0.510 0.530 0.005 0 0.510 0.530 0.016 0.063 REF T DATUM PLANE -H- R K W X DETAIL C Q Technical Data 140 MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 Mechanical Specifications MOTOROLA Technical Data -- MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A SC05C8A Section 15. Ordering Information 15.1 Contents 15.2 15.3 15.4 15.5 15.6 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 MCU Ordering Forms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 Application Program Media. . . . . . . . . . . . . . . . . . . . . . . . . . .142 ROM Program Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 ROM Verification Units (RVUs). . . . . . . . . . . . . . . . . . . . . . . . 143 15.2 Introduction This section contains instructions for ordering custom-masked read-only memory (ROM) microcontroller units (MCU). 15.3 MCU Ordering Forms To initiate an order for a ROM-based MCU, first obtain the current ordering form for the MCU from a Motorola representative. Submit these items when ordering MCUs: * * * A current MCU ordering form that is completely filled out (Contact your Motorola sales office for assistance.) A copy of the customer specification if the customer specification deviates from the Motorola specification for the MCU. Customer's application program on one of the media listed in 15.4 Application Program Media. MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 MOTOROLA Ordering Information Technical Data 141 Ordering Information 15.4 Application Program Media Please deliver the application program to Motorola in one of these media: * * * Macintosh(R)(1) 3-1/2-inch diskette (double-sided 800 K or double-sided high-density 1.4 M) MS-DOS(R)(2) or PC-DOSTM(3) 3-1/2-inch diskette (double-sided 720 K or double-sided high-density 1.44 M) MS-DOS(R) or PC-DOSTM 5-1/4-inch diskette (double-sided double-density 360 K or double-sided high-density 1.2 M) Use positive logic for data and addresses. When submitting the application program on a diskette, clearly label the diskette with this information: * * * * * * * Customer name Customer part number Project or product name File name of object code Date Name of operating system that formatted diskette Formatted capacity of diskette On diskettes, the application program must be in Motorola's S-record format (S1 and S9 records), a character-based object file format generated by M6805 cross assemblers and linkers. Begin the application program at the first user ROM location. Program addresses must correspond exactly to the available on-chip user ROM addresses as shown in the memory map. Write $00 in all non-user ROM locations or leave all non-user ROM locations blank. Refer to the current MCU ordering form for additional requirements. Motorola may request pattern re-submission if non-user areas contain any non-zero code. 1. Macintosh is a registered trademark of Apple Computer, Inc. 2. MS-DOS is a registered trademark of Microsoft Corporation. 3. PC-DOS is a trademark of International Business Machines Corporation. Technical Data 142 MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 Ordering Information MOTOROLA Ordering Information ROM Program Verification If the memory map has two user ROM areas with the same addresses, then write the two areas in separate files on the diskette. Label the diskette with both filenames. In addition to the object code, a file containing the source code can be included. Motorola keeps this code confidential and uses it only to expedite ROM pattern generation in case of any difficulty with the object code. Label the diskette with the filename of the source code. 15.5 ROM Program Verification The primary use for the on-chip ROM is to hold the customer's application program. The customer develops and debugs the application program and then submits the MCU order along with the application program. Motorola inputs the customer's application program code into a computer program that generates a listing verify file. The listing verify file represents the memory map of the MCU. The listing verify file contains the user ROM code and may also contain non-user ROM code, such as self-check code. Motorola sends the customer a computer printout of the listing verify file along with a listing verify form. To aid the customer in checking the listing verify file, Motorola will program the listing verify file into customer-supplied blank preformatted Macintosh or DOS disks. All original pattern media are filed for contractual purposes and are not returned. Check the listing verify file thoroughly, then complete and sign the listing verify form and return the listing verify form to Motorola. The signed listing verify form constitutes the contractual agreement for the creation of the custom mask. 15.6 ROM Verification Units (RVUs) After receiving the signed listing verify form, Motorola manufactures a custom photographic mask. The mask contains the customer's application program and is used to process silicon wafers. The MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 MOTOROLA Ordering Information Technical Data 143 Ordering Information application program cannot be changed after the manufacture of the mask begins. Motorola then produces 10 MCUs, called RVUs, and sends the RVUs to the customer. RVUs are usually packaged in unmarked ceramic and tested to 5 Vdc at room temperature. RVUs are not tested to environmental extremes because their sole purpose is to demonstrate that the customer's user ROM pattern was properly implemented. The 10 RVUs are free of charge with the minimum order quantity. These units are not to be used for qualification or production. RVUs are not guaranteed by Motorola Quality Assurance. Technical Data 144 MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 Ordering Information MOTOROLA Technical Data -- MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A Appendix A. MC68HCL05C8A A.1 Contents A.2 A.3 A.4 A.5 A.6 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 Low-Power Operating Temperature Range . . . . . . . . . . . . . . 145 2.5-V to 3.6-V DC Electrical Characteristics . . . . . . . . . . . . . 146 1.8-V to 2.4-V DC Electrical Characteristics . . . . . . . . . . . . . . 146 Low-Power Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . 147 A.2 Introduction This appendix introduces the MC68HCL05C8A, a low-power version of the MC68HC05C8A. The technical data applying to the MC68HC05C8A applies to the MC68HCL05C8A with the exceptions given here. A.3 Low-Power Operating Temperature Range mperature The follow data replaces the corresponding data found in 13.4 Operating Temperature Range. Rating Operating temperature range(1) MC68HCL05C8AP, FN, B, FB 1. P = Plastic dual in-line package (PDIP) FN = Plastic-leaded chip carrier (PLCC) B = Shrink dual in-line package (SDIP) FB = Quad flat pack (QFP) Symbol TA Value TL to TH 0 to +70 Unit C MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 MOTOROLA MC68HCL05C8A Technical Data 145 MC68HCL05C8A A.4 2.5-V to 3.6-V DC Electrical Characteristics Characteristic Output high voltage (ILoad = -0.2 mA) PA7-PA0, PB7-PB0, PC6-PC0, TCMP (ILoad = -0.4 mA) PD4-PD1 (ILoad = -1.5 mA) PC7 Output low voltage (ILoad = 0.4 mA) PA7-PA0, PB7-PB0, PC6-PC0, PD4-PD1, TCMP (ILoad = 5.0 mA) PC7 Input pullup current PB7-PB0 (with pullup) 1. VDD = 2.5-3.6 Vdc Symbol Min(1) VDD - 0.3 VDD - 0.3 VDD - 0.3 Typ Max Unit VOH -- -- -- -- -- -- V VOL -- -- 40 -- -- 160 0.3 0.3 300 V Iin A A.5 1.8-V to 2.4-V DC Electrical Characteristics Characteristic Output high voltage (ILoad = -0.1 mA) PA7-PA0, PB7-PB0, PC6-PC0, TCMP (ILoad = -0.2 mA) PD4-PD1 (ILoad = -0.75 mA) PC7 Output low voltage (ILoad = 0.2 mA) PA7-PA0, PB7-PB0, PC6-PC0, PD4-PD1, TCMP (ILoad = 2.0 mA) PC7 Input pullup current PB7-PB0 (with pullup) 1. VDD = 2.5-3.6 Vdc Symbol Min(1) VDD - 0.3 VDD - 0.3 VDD - 0.3 Typ Max Unit VOH -- -- -- -- -- -- V VOL IIn -- -- 15 -- -- 110 0.3 0.3 200 V A Technical Data 146 MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 MC68HCL05C8A MOTOROLA MC68HCL05C8A Low-Power Supply Current A.6 Low-Power Supply Current w-Power Characteristic(1) Supply current (4.5-5.5 Vdc @ fBus = 2.1 MHz) Run(2) Wait(3) Stop(4) 25C 0C to +70C (standard) Supply current (2.4-3.6 Vdc @ fBus = 1.0 MHz) Run(2) Wait(3) Stop(4) 25C 0C to +70 C (standard) Supply current (2.5-3.6 Vdc @ fBus = 500 kHz) Run(2) Wait(3) Stop(4) 25C 0C to +70C (standard) Supply current (1.8-2.4 Vdc @ fBus = 500 kHz) Run(2) Wait(3) Stop(4) 25C 0C to +70C (standard) IDD -- -- -- -- 300 250 1 -- 600 400 2 5 IDD -- -- -- -- 500 300 1 -- 750 500 5 10 IDD -- -- -- -- 1.00 0.7 1 -- 1.4 1.0 5 10 mA mA IDD -- -- -- -- 3.50 1.6 1 -- 4.25 2.25 15 25 mA mA Symbol Min Typ(1) Max Unit A A A A A A A A A A A A 1. Typical values reflect measurements taken on average processed devices at the midpoint of voltage range, 25C only. 2. Run (operating) IDD measured using external square wave clock source; all I/O pins configured as inputs, Port B = VDD, all other inputs VIL = 0.2 V, VIH = VDD -0.2 V; no DC loads; less than 50 pF on all outputs; CL = 20 pF on OSC2 3. Wait IDD measured using external square wave clock source; all I/O pins configured as inputs, Port B = VDD, all other inputs VIL = 0.2 V, VIH = VDD -0.2 V; no DC loads; less than 50 pF on all outputs; CL = 20 pF on OSC2. Wait IDD is affected linearly by the OSC2 capacitance. 4. Stop IDD measured with OSC1 = 0.2 V; all I/O pins configured as inputs, Port B = VDD, all other inputs VIL = 0.2 V, VIH = VDD -0.2 V MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 MOTOROLA MC68HCL05C8A Technical Data 147 MC68HCL05C8A Technical Data 148 MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 MC68HCL05C8A MOTOROLA Technical Data -- MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A Appendix B. MC68HSC05C8A B.1 Contents B.2 B.3 B.4 B.5 B.6 B.7 B.8 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 High-Speed Operating Temperature Range. . . . . . . . . . . . . . 149 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 150 4.5-V to 5.5-V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . 151 2.4-V to 3.6-V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . 152 4.5-V to 5.5-V High-Speed SPI Timing . . . . . . . . . . . . . . . . . . 153 2.4-V to 3.6-V High-Speed SPI Timing . . . . . . . . . . . . . . . . . . 154 B.2 Introduction duction This appendix introduces the MC68HSC05C8A, a high-speed version of the MC68HC05C8A. The technical data applying to the MC68HC05C8A applies to the MC68HSC05C8A with the exceptions given here. B.3 High-Speed Operating Temperature Range The follow data replaces the corresponding data found in 13.4 Operating Temperature Range. Rating Operating temperature range(1) MC68HSC05C8AP, FN, B, FB MC68HSC05C8CP, CFN, CB, CFB 1. P = Plastic dual in-line package (PDIP) FN = Plastic-leaded chip carrier (PLCC) B = Shrink dual in-line package (SDIP) FB = Quad flat pack (QFP) Symbol TA Value TL to TH 0 to +70 -40 to +85 Unit C MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 MOTOROLA MC68HSC05C8A Technical Data 149 MC68HSC05C8A B.4 DC Electrical Characteristics The data in 13.7 5.0-V DC Electrical Characteristics and 13.8 3.3-V DC Electrical Characteristics applies to the MC68HSC05C8A with the exceptions given here. Characteristic(1) Supply current (4.5-5.5 Vdc @ fBUS = 4.0 MHz) Run(2) Wait(3) Stop(4) 25C 0C to 70C (Standard) -40C to 125C (Standard) Supply Current (2.4-3.6 Vdc @ fBUS = 2.0 MHz) Run(2) Wait(3) Stop(4) 25C 0C to 70C (standard) -40C to 125C (standard) Input pullup current (VDD = 4.5-5.5 V) PB7-PB0 (with pullup) Input pullup current (VDD = 2.4-3.6 V) PB7-PB0 (with pullup) -- -- IDD -- -- -- IIn IIn 175 50 1 -- -- 385 160 8 16 20 750 350 2.50 1.00 4.00 2.00 mA mA -- -- IDD -- -- -- 1 -- -- 20 40 50 7.00 2.00 11.0 6.50 mA mA Symbol Min Typ Max Unit A A A A A A A A 1. Typical values reflect measurements taken on average processed devices at the midpoint of voltage range, 25C only. 2. Run (operating) IDD measured using external square wave clock source; all I/O pins configured as inputs, Port B = VDD, all other inputs VIL = 0.2 V, VIH = VDD-0.2 V; no DC loads; less than 50 pF on all outputs; CL = 20 pF on OSC2 3. Wait IDD measured using external square wave clock source; all I/O pins configured as inputs, Port B = VDD, all other inputs VIL = 0.2 V, VIH = VDD -0.2 V; no DC loads; less than 50 pF on all outputs; CL = 20 pF on OSC2. Wait IDD is affected linearly by the OSC2 capacitance. 4. Stop IDD measured with OSC1 = 0.2 V; all I/O pins configured as inputs, Port B = VDD, all other inputs VIL = 0.2 V, VIH = VDD -0.2 V Technical Data 150 MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 MC68HSC05C8A MOTOROLA MC68HSC05C8A 4.5-V to 5.5-V Control Timing B.5 4.5-V to 5.5-V Control Timing The data in 13.9 5.0-V Control Timing applies to the MC68HSC05C8A with the exceptions given here. Characteristic Oscillator frequency Crystal External Clock Internal operating frequency (fOSC / 2) Crystal External clock Cycle time Crystal oscillator startup time Stop recovery startup time RESET pulse width Timer Resolution(1) Input capture pulse width Input capture pulse width Interrupt pulse width low (edge-triggered) Interrupt pulse period OSC1 pulse width Symbol fOSC Min -- dc -- dc 244 Max 8.2 8.2 4.1 4.1 -- 100 100 1.5 -- Unit MHz fOP tCYC tOXOV tILCH tRL tRESL tTH or tTL tTHTL tILIH tILIL tOH or tOL MHz ns ms ms tCYC tCYC ns tCYC ns tCYC ns 4.0 64 (2) -- -- -- -- -- -- 64 (3) 50 1. Because a 2-bit prescaler in the timer must count four internal cycles (tCYC), this is the limiting minimum factor in determining the timer resolution. 2. The minimum period tTLTL should not be less than the number of cycle times it takes to execute the capture interrupt service routine plus 24 tCYC. 3. The minimum tILIL should not be less than the number of cycle times it takes to execute the interrupt service routine plus 19 tCYC. MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 MOTOROLA MC68HSC05C8A Technical Data 151 MC68HSC05C8A B.6 2.4-V to 3.6-V Control Timing The data in 13.10 3.3-V Control Timing applies to the MC68HSC05C8A with the exceptions given here. Characteristic Oscillator frequency Crystal External clock Internal operating frequency (fOSC / 2) Crystal External clock Cycle time Crystal oscillator startup time Stop recovery startup time RESET pulse width Timer Resolution(1) Input capture pulse width Input capture pulse width Interrupt pulse width low (edge-triggered) Interrupt pulse period OSC1 pulse width Symbol fOSC Min -- dc -- dc 480 Max 4.2 4.2 2.1 2.1 -- 100 100 1.5 -- Unit MHz fOP tCYC tOXOV tILCH tRL tRESL tTH or tTL tTHTL tILIH tILIL tOH or tOL MHz ns ms ms tCYC tCYC ns tCYC ns tCYC ns 4.0 125 (2) -- -- -- -- -- -- 125 (3) 90 1. Because a 2-bit prescaler in the timer must count four internal cycles (tCYC), this is the limiting minimum factor in determining the timer resolution. 2. The minimum period tTLTL should not be less than the number of cycle times it takes to execute the capture interrupt service routine plus 24 tCYC. 3. The minimum tILIL should not be less than the number of cycle times it takes to execute the interrupt service routine plus 19 tCYC. Technical Data 152 MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 MC68HSC05C8A MOTOROLA MC68HSC05C8A 4.5-V to 5.5-V High-Speed SPI Timing B.7 4.5-V to 5.5-V High-Speed SPI Timing d The data in 13.11 5.0-V Serial Peripheral Interface Timing applies to the MC68HSC05C8A with the exceptions given here. Num Operating frequency Master Slave 1 Cycle time Master Slave Enable lead time Master Slave Enable lag time Master Slave Clock (SCK) high time Master Slave Clock (SCK) low time Master Slave Data setup time (inputs) Master Slave Data hold time (inputs) Master Slave Slave access time (time to data active from high-impedance state) Slave disable time (hold time to high-impedance state) Data valid Master (before capture edge) Slave (after enable edge)(2) Data hold time (outputs) Master (after capture edge) Slave (After Enable Edge) Rise time (20% VDD to 70% VDD, CL = 200 pF) SPI outputs (SCK, MOSI, and MISO) SPI inputs (SCK, MOSI, MISO, and SS) Fall time (70% VDD to 20% VDD, CL = 200 pF) SPI outputs (SCK, MOSI, and MISO) SPI inputs (SCK, MOSI, MISO, and SS) Characteristic Symbol fOP(M) fOP(S) tCYC(M) tCYC(S) tLead(M) tLead(S) tLag(M) tLag(S) tW(SCKH)M tW(SCKH)S tW(SCKL)M tW(SCKL)S tSU(M) tSU(S) tH(M) tH(S) tA tDIS tV(M) tV(S) tHO(M) tHO(S) tRM tRS tFM tFS Min dc dc 2.0 244 (1) Max 0.5 4.1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 61 122 -- 122 -- -- 50 1.0 50 1.0 Unit fOP MHz tCYC ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns tCYC(M) ns tCYC(M) ns ns s ns s 2 122 (1) 3 366 166 93 166 93 49 49 49 49 0 -- 0.25 -- 0.25 0 -- -- -- -- 4 5 6 7 8 9 10 11 12 13 1. Signal production depends on software. 2. Assumes 200 pF load on all SPI pins. MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 MOTOROLA MC68HSC05C8A Technical Data 153 MC68HSC05C8A B.8 2.4-V to 3.6-V High-Speed SPI Timing The data in 13.12 3.3-V Serial Peripheral Interface Timing applies to the MC68HSC05C8A with the exceptions given in the following table. Num Operating frequency Master Slave 1 Cycle time Master Slave Enable lead time Master Slave Enable lag time Master Slave Clock (SCK) High Time Master Slave Clock (SCK) low time Master Slave Data setup time (Inputs) Master Slave Data hold time (Inputs) Master Slave Slave access time (time to data active from high-impedance state) Slave disable time (hold time to high-impedance state) Data Master (before capture edge) Slave (after enable edge)(2) Data Hold Time (outputs) Master (after capture edge) Slave (after enable edge) Rise time (20% VDD to 70% VDD, CL = 200 pF) SPI outputs (SCK, MOSI, and MISO) SPI inputs (SCK, MOSI, MISO, and SS) Fall time (70% VDD to 20% VDD, CL = 200 pF) SPI outputs (SCK, MOSI, and MISO) SPI inputs (SCK, MOSI, MISO, and SS) Characteristic Symbol fOP(M) fOP(S) tCYC(M) tCYC(S) tLead(M) tLead(S) tLag(M) tLag(S) tW(SCKH)M tW(SCKH)S tW(SCKL)M tW(SCKL)S tSU(M) tSU(S) tH(M) tH(S) tA tDIS tV(M) tV(S) tHO(M) tHO(S) tRM tRS tFM tFS Min dc dc 2.0 480 (1) Max 0.5 2.1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 120 240 -- 240 -- -- 100 2.0 100 2.0 Unit fOP MHz tCYC ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns tCYC(M) ns tCYC(M) ns ns s ns s 2 240 (1) 3 720 340 190 340 190 100 100 100 100 0 -- 0.25 -- 0.25 0 -- -- -- -- 4 5 6 7 8 9 10 11 12 13 1. Signal production depends on software. 2. Assumes 20 pF load on all SPI pins. Technical Data 154 MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 MC68HSC05C8A MOTOROLA Technical Data -- MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A Appendix C. M68HC05Cx Family Feature Comparisons y Refer to Table C-1 for a comparison of the features for all the M68HC05C Family members. MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 MOTOROLA M68HC05Cx Family Feature Comparisons Technical Data 155 Technical Data MC68HC05C8A * MC68HCL05C8A * MC68HSC05C8A -- Rev. 5.0 M68HC05Cx Family Feature Comparisons 156 M68HC05Cx Family Feature Comparisons MOTOROLA Table C-1. M68HC05Cx Feature Comparison C4 USER ROM USER EPROM CODE SECURITY RAM OPTION REGISTER (IRQ/RAM/ SEC) MASK OPTION REGISTER(S) PORTB KEYSCAN (PULLUP/ INTERRUPT) PC7 DRIVE 4160 -- NO 176 C4A 4160 -- YES 176 705C4A -- 4160 YES 176 $1FDF (IRQ/SEC) C8 7744 -- NO 176 C8A 7744 -- YES 176 705C8 -- 7596-7740 YES 176-304 $1FDF (IRQ/RAM/ SEC) NO 705C8A -- 7596-7740 YES 176-304 $1FDF (IRQ/RAM/SEC) C12 12,096 -- NO 176 C12A 12,096 -- YES 176 C9 15,760-15,936 -- NO 176-352 $3FDF (IRQ/RAM) C9A 15,760-15,936 -- YES 176-352 $3FDF (IRQ/RAM) 705C9 -- 15,760-15,936 NO 176-352 $3FDF (IRQ/RAM) 705C9A -- 12,096-15,936 YES 176-352 $3FDF (IRQ/RAM) NO NO NO NO NO NO NO NO YES MASK OPTION HIGH CURRENT $1FF0-1 YES MOR SELECTABLE HIGH CURRENT NO NO YES MASK OPTION HIGH CURRENT PD7, 5-0 INPUT ONLY YES MASK OPTION 64 ms (@4 MHz osc) $1FF0-1 YES MOR SELECTABLE HIGH CURRENT PD7, 5-0 INPUT ONLY TWO TYPES SOFTWARE+ MOR SOFTWARE+ MOR SELECTABLE WRITE $55/$AA TO $001D OR CLR $1FF0 YES PROGRAMMABLE COP/CLOCK MONITOR NO NO YES MASK OPTION HIGH CURRENT PD7, 5-0 INPUT ONLY YES MASK OPTION NO YES MASK OPTION HIGH CURRENT PD7, 5-0 INPUT ONLY YES MASK OPTION NO NO YES MASK OPTION HIGH CURRENT PD7, 5-0 BIDIRECTIONAL YES SOFTWARE SOFTWARE SELECTABLE NO $3FF0-1 YES MOR SELECTABLE HIGH CURRENT PD7, 5-0 BIDIRECTIONAL TWO TYPES SOFTWARE+ MOR SOFTWARE+ MOR SELECTABLE WRITE $55/$AA TO $001D OR CLR $3FF0 YES (C9A MODE) POR/C9A COP/ CLOCK MONITOR MOR SELECTABLE (C12A MODE) NO NO NO NO NO STANDARD STANDARD PD7, 5-0 INPUT ONLY NO -- STANDARD PD7, 5-0 INPUT ONLY YES SOFTWARE SOFTWARE SELECTABLE STANDARD PD7, 5-0 BIDIRECTIONAL YES SOFTWARE SOFTWARE SELECTABLE STANDARD PD7, 5-0 BIDIRECTIONAL YES SOFTWARE SOFTWARE SELECTABLE PORT D COP COP ENABLE PD7, 5-0 PD7, 5-0 PD7, 5-0 INPUT ONLY INPUT ONLY INPUT ONLY NO -- YES MASK OPTION 64 ms (@4 MHz osc) YES MOR 64 ms (@4 MHz osc) COP TIMEOUT -- -- 64 ms 64 ms (@4 MHz osc) (@4MHz osc) COP CLEAR -- CLR $1FF0 CLR $1FF0 -- CLR $1FF0 WRITE $55/$AA TO $001D CLR $3FF0 CLR $3FF0 WRITE $55/$AA WRITE $55/$AA WRITE $55/$AA TO $001D TO $001D TO $001D CLOCK MONITOR ACTIVE RESET NO NO NO NO NO YES NO NO YES POR/COP/ CLOCK MONITOR YES POR/COP/ CLOCK MONITOR YES POR/COP/ CLOCK MONITOR NO NO NO NO NO COP/CLOCK MONITOR NO NO STOP DISABLE NO MASK OPTION NO NO MASK OPTION NO MASK OPTION MASK OPTION NO NO NO NOTES: 1. The expanded RAM map (from $30-$4F and $100-$15F) available on the OTP devices MC68HC705C8 and MC68HC705C8A is not available on the ROM devices MC68HC05C8 and MC68HC05C8A. 2. The programmable COP available on the MC68HC705C8 and MC68HC705C8A is not available on the MC68HC05C8A. For ROM compatibility, use the non-programmable COP. HOW TO REACH US: USA/EUROPE/LOCATIONS NOT LISTED: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado 80217 1-303-675-2140 or 1-800-441-2447 JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3-20-1, Minami-Azabu Minato-ku, Tokyo 106-8573 Japan 81-3-3440-3569 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong 852-26668334 TECHNICAL INFORMATION CENTER: 1-800-521-6274 HOME PAGE: http://www.motorola.com/semiconductors Information in this document is provided solely to enable system and software implementers to use Motorola products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and the Stylized M Logo are registered in the U.S. Patent and Trademark Office. digital dna is a trademark of Motorola, Inc. All other product or service names are the property of their respective owners. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. (c) Motorola, Inc. 2002 MC68HC05C8A/D |
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